【Verilog语法006】$fwrite文件操作

integer handle      ;
always @(posedge clk)begin
    if(rst) begin
        handle = $fopen("data.txt");
        $fdisplay(handle,"%h",16'h2);
        $fclose(handle);
    end else if(  )begin
        handle = $fopen("data.txt","a+");
        $fdisplay(handle,"%h",16'h2);
        $fclose(handle);
    end
end

`timescale 1ns / 1ps
 
module file_test(
 
    );
reg [3:0]data[0:15];
reg [3:0]data2[0:15];
integer handle1;
integer i=0;
initial
begin
    $readmemb("num.txt",data);//默认文件在工程所在路径目录
 
    handle1 = $fopen("num2.txt","w");
    repeat(16)
    begin
        $fwrite(handle1,"%d\n",data[15-i]);
        i = i+1;
    end
    $fclose(handle1);
end
endmodule

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