verilog的冒泡数据排列

verilog的冒泡数据排列

有所借鉴

module my_sort #(
					parameter D_WIDTH = 16,
					parameter D_DEPTH = 256,
					)
(
					clk,    // Clock
					rst_n,  // Asynchronous reset active low
					D_in,
					D_out,
					in_over,
					out_over
);

input   				clk;
input   				rst_n;
input	[D_WIDTH-1:0]	D_in;
output	[D_WIDTH-1:0]	D_out;
output					in_over;
output					out_over;

reg		[D_WIDTH-1:0]	D_mem [D_DEPTH-1:0]
integer	i,j,m;

task exchange();
	inout [D_WIDTH-1] x,y;
	reg [D_WIDTH-1] temp;

	begin
		if (x<y) begin
			begin 
				temp=x;
				x=y;
				y=temp;
			end
		end
	end

endtask : exchange

always @(posedge clk or negedge rst_n) begin
	if(~rst_n) begin
		i <= 0;
		j <= 0;
		m <= 0;
		in_over<=0;
	end else begin
		if (m<D_DEPTH-1) begin
			D_mem<=D_in;
			m<=m+1;
		end
		else if (m==D_DEPTH-1)begin
			if (i<D_DEPTH) begin
				for (i = 0; i < D_DEPTH; i++) begin
					for (j = 0; j < D_DEPTH-1-i; j++) begin
						exchange(D_mem[j+1],D_mem[j]);
					end
				end
			end
			else if (i==D_DEPTH-1)begin 
				in_over<=1;
			end
		end
	end
end

integer k;

always @(posedge clk or negedge rst_n) begin
	if(~rst_n) begin
		k <= 0;
		D_out<=0;
	end else begin
		if (in_over==1) begin
			if (k==D_DEPTH-1) begin
				out_over<=1;
			end
			else begin
				D_out<=D_mem[k];
				k<=k+1;
			end	
		end
	end
end

endmodule