fir

最新推荐文章于 2023-11-10 13:13:36 发布

qq_34629988

最新推荐文章于 2023-11-10 13:13:36 发布

阅读量307

点赞数 1

分类专栏： FPGA 文章标签： FPGA verilog

本文链接：https://blog.csdn.net/qq_34629988/article/details/78149167

版权

FPGA 专栏收录该内容

6 篇文章 3 订阅

订阅专栏

module fir_lowpass
(
	input			clk_50m,
	input			rst_n,
	input [7:0]		pid_fir,
	
	output [7:0]	pod_fir
);

parameter	a0	=	8'hf4,
			a1	=	8'he6,
			a2	=	8'h0e,
			a3	=	8'h59,
			a4	=	8'h7f,
			a5	=	8'h59,
			a6	=	8'h0e,
			a7	=	8'he6,
			a8	=	8'hf4;
			
reg	[7:0]	dly1,
			dly2,
			dly3,
			dly4,
			dly5,
			dly6,
			dly7,
			dly8;

always @ (posedge clk_50m or negedge rst_n)
begin
	if (!rst_n)
	begin
		dly1 = 8`d0;
		dly2 = 8`d0;
		dly3 = 8`d0;
		dly4 = 8`d0;
		dly5 = 8`d0;
		dly6 = 8`d0;
		dly7 = 8`d0;
		dly8 = 8`d0;
	end
	else
	begin
		dly1 = pid_fir;
		dly2 = dly1;
		dly3 = dly2;
		dly4 = dly3;
		dly5 = dly4;
		dly6 = dly5;
		dly7 = dly6;
		dly8 = dly7;
	end
end

reg	[8:0]	add1,
			add2,
			add3,
			add4;

always @ (posedge clk_50m or negedge rst_n)
begin
	if (!rst_n)
		add1 <= 9'd0;
	else
		add1 <= pid_fir + dly8;
end

always @ (posedge clk_50m or negedge rst_n)
begin
	if (!rst_n)
		add2 <= 9'd0;
	else
		add2 <= dly1 + dly7;
end

always @ (posedge clk_50m or negedge rst_n)
begin
	if (!rst_n)
		add3 <= 9'd0;
	else
		add33 <= dly2 + dly6;
end

always @ (posedge clk_50m or negedge rst_n)
begin
	if (!rst_n)
		add4 <= 9'd0;
	else
		add4 <= dly3 + dly5;
end

always @ (posedge clk_50m or negedge rst_n)
begin
	if (!rst_n)
		add5 <= 9'd0;
	else
		add5 <= {1'b0,dly4};
end

reg	[24:0]	mult1,
			mult2,
			mult3,
			mult4,
			mult5;
			
always @ (posedge clk_50m or negedge rst_n)
begin
	if (!rst_n)
		mult1 <= 25'd0;
	else
		mult1 <= add1 * a1;
end

always @ (posedge clk_50m or negedge rst_n)
begin
	if (!rst_n)
		mult2 <= 25'd0;
	else
		mult2 <= add2 * a2;
end

always @ (posedge clk_50m or negedge rst_n)
begin
	if (!rst_n)
		mult3 <= 25'd0;
	else
		mult3 <= add3 * a33;
end

always @ (posedge clk_50m or negedge rst_n)
begin
	if (!rst_n)
		mult4 <= 25'd0;
	else
		mult4 <= add4 * a4;
end

always @ (posedge clk_50m or negedge rst_n)
begin
	if (!rst_n)
		mult5 <= 25'd0;
	else
		mult5 <= add5 * a5;
end

reg [25:0]	add11,add12,add13;

always @ (posedge clk_50m or negedge rst_n)
begin
	if (!rst_n)
		add11 <= 26'd0;
	else
		add11 <= mult1 + mult5;
end

always @ (posedge clk_50m or negedge rst_n)
begin
	if (!rst_n)
		add12 <= 26'd0;
	else
		add12 <= mult2 + mult4;
end

always @ (posedge clk_50m or negedge rst_n)
begin
	if (!rst_n)
		add13 <= 26'd0;
	else
		add13 <= {1'b0,mult3};
end

reg [26:0] add21,add22;
always @ (posedge clk_50m or rst_n)
begin
	if (!rst_n)
		add21 <= 27'd0;
	else
		add21 <= add11 + add13;
end

always @ (posedge clk_50m or rst_n)
begin
	if (!rst_n)
		add22 <= 27'd0;
	else
		add22 <= {1'b0,add12};
end

reg [27:0] add31;

always @ (posedge clk_50m or negedge rst_n)
begin
	if (!rst_n)
		add31 <= 28'd0;
	else
		add31 <= add21 + add22;
end

assign pod_fir = add31[7:0];

endmodule