二选一多路选择器
二选一多路选择器真值表:
a b s y
* * 1 b
* * 0 a
VHDL描述:
1、顺序语句结构:
library ieee;
use ieee.std_logic_1164.all;
entity mux21a is
port(a,b:in bit;
s:in bit;
y:out bit);
end entity mux21a;
architecture one of mux21a is
begin
y <= a when s = '0' else b;
end architecture one;
2、并行语句结构:
library ieee;
use ieee.std_logic_116