ZYNQ flash在QSPI模式下不能下载，下载后不能正常运行

ZYNQ flash在QSPI模式下不能下载，下载后不能正常运行

在AR# 70548文档介绍：烧写FLSASH尽管强烈推荐使用JTAG引导模式，但是对于以QSPI模式启动的设备有一个解决方案：
新建在FSBL工程（新建，和之前用来生成BOOT.BIN用的fsbl.elf不是同一个）mian.c文件中main函数383行后面增加BootModeRegister = JTAG_MODE; （位置不要放错，其他函数也有类似的位置）。编译成又一个FSBL_Loader.elf文件。这个是用来下载的，之前那个是用来合成BOOT.BIN的。

在FSBL工程fsbl_debug.h文件中53行后面增加#define FSBL_DEBUG_INFO 可在串口查看fsbl运行状态。
刚开始发现每次下载前要重新上电才能下载成功。后来发现好像没必要。
下载的时候把两个校验勾选上。我刚开始没勾选，如果硬件有问题也能下载成功了但是不能正常运行。

XILINX 官网的两个问答记录：

AR# 70548
QSPI模式下下载程序失败：
Initialization done, programming the memory
BOOT_MODE REG = 0x00000001
WARNING: [Xicom 50-100] The current boot mode is QSPI.
尽管强烈推荐使用JTAG引导模式，但是对于以qspi引导模式启动的设备有一个解决方案。
从2017.3开始，为Zynq-7000编写flash需要指定一个FSBL。参见(Xilinx回答70148)。
如果在QSPI引导模式下启动，这个FSBL将尝试从flash加载分区，从而导致flash编程的错误行为。
创建一个新的FSBL项目，并添加以下更改(main.c)，将其用于SDK中的Flash编程。
/*

• Read bootmode register
  */
  BootModeRegister = Xil_In32(BOOT_MODE_REG);
  BootModeRegister &= BOOT_MODES_MASK;
  //add this line to trick boot mode to JTAG
  BootModeRegister = JTAG_MODE;
  这将防止FSBL在编程运行时从Flash设备加载任何现有分区。

AR# 70148

2017.3 Zynq-7000 SoC: QSPI flash programming now requires that you specify an FSBL
如果使用 Vivado 2019.1 及以后版本就不需要这个定制的 fsbl，用自己生成的 fsbl 即
可。
Solution
With this change there are a number of implications:

1. The user needs a working FSBL.
   If this FSBL is initializing DDR, then DDR needs to be functioning even if the QSPI flash programming does not really use it.
   A suggestion is to use #define FSBL_DEBUG_INFO in the FSBL, to check if the UART of the FSBL is fully executed without hangs during QSPI flash programming.
2. If you have issues programming the FLASH in Vivado 2017.3 or 2017.4, add the following environment variable.
   (The ENV variable is not required for 2018.1):
   XIL_CSE_ZYNQ_UBOOT_QSPI_FREQ_HZ = 10000000
   This will force the mini-uBoot to set the QSPI device clock to 10 MHz.
   Note: depending on your FSBL design, you might see a different QSPI clock on your hardware.
3. The device clocking is now configured by the FSBL rather than the tool.
   The configuration which was previously used by the tool is listed below.
   If you have issues programming the flash, you should check the FSBL configuration against this table.
   Register Name Register Address Register Value
   ARM_PLL_CFG 0xF8000110 0x00177EA0 (default values)
   ARM_PLL_CTRL 0xF8000100 0x0001A000 ARM_PLL = 866 MHz (not bypassed)
   ARM_CLK_CTRL 0xF8000120 0x1F000400 CPU_6x4x = 866 / 4 = 216 MHz
   IO_PLL_CFG 0xF8000118 0x00177EA0 (default values)
   IO_PLL_CTRL 0xF8000108 0x0001A000 IO_PLL = 866 MHz (not bypassed)
   PLL_STATUS 0xF800010C 0x0000003F ARM_PLL and IO_PLL are LOCKED and STABLE.

• Assuming PS_REF_CLK = 33.33 MHz

4. In case of XIP (Execute in place from QSPI), a custom FSBL that executes from OCM needs to be created to be specified during QSPI flash programming.