VHDL实现FIFO

FIFO

FIFO缓冲器经常使用在很多设计中，成为连接具有相同或者不同时钟的子系统的桥梁，来达到临时访问的要求。
下面的代码实现的是深度8字，宽度9bits的的FIFO，包含组合和同步逻辑设计。

代码

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fifo89 is
    Port (     	
    	clk : in std_logic;
        rst : in std_logic;
        rd : in std_logic;
        wr : in std_logic;
        rdinc : in std_logic;
        wrinc : in std_logic;
        rdptrclr : in std_logic;
        wrptrclr : in std_logic;
        data_in : in std_logic_vector(8 downto 0);
        data_out : out std_logic_vector(8 downto 0));
end fifo89;

-- clk: used to synchronize the buffers;
-- rst: reset the buffers
-- rd: when valid, the output buffers are enabled;
-- wr: when valid, write register with 9-bit width is permitted; 
-- rdinc: read counter enabled;
-- wrinc: write counter enabled;
-- rdptrclr: reset read counter, pointing to the first register for
-- read purpose;
-- wrptrclr: reset write counter, pointing to the first register for
-- write purpose;
-- data_in: data inputs with 9-bit width to the FIFOs;
-- data_out: data outputs with 9-bit width from the FIFOs.

architecture Behavioral of fifo89 is
	type fifo_array is array(7 downto 0) of std_logic_vector(8 downto 0);
	signal fifo: fifo_array;
	signal wrptr, rdptr: std_logic_vector(2 downto 0);
	signal en: std_logic_vector( 7 downto 0);
	signal dmuxout: std_logic_vector(8 downto 0);

begin
	
-- fifo register_array:
reg_array: process (rst, clk)
	begin
		if rst = '1' then
			for i in 7 downto 0 loop
				fifo(i) <