开始抢答开关打开后,led全亮,抢答成功后对应的led灭。复位或重新开始,开始新一轮抢答
module qiang_4(
input wire clk ,
input wire rst ,
input wire start ,
input wire [3:0] key ,
output reg [3:0] led
);
reg [3:0] key_buffer = 0 ;
always@(posedge clk,negedge rst)
begin
if(!rst||start==0)begin
key_buffer<=4'b0000;
end
else if(key!=4'b0000 && key_buffer==0)
key_buffer<=key;
else
key_buffer<=key_buffer;
end
always@(posedge clk,negedge rst)
begin
if(!rst)
led<=4'b0000;
else if(start==1)
led<=key_buffer^4'b1111;
else
led<=4'b0000;
end
endmodule