verilog流水灯

module led(
       clk,rst_n,          //50Mhz
       led_show
);
input clk,rst_n;
output reg [26:0] led_show;
//--------------分频1000*1000*25--------------
reg [9:0] cnt1;
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n) cnt1<=10'b0;
    else if(cnt1==1000) cnt1<=10'b0;
    else cnt1<=cnt1+1'b1;
end

reg [9:0] cnt2;
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n) cnt2<=10'b0;
    else if(cnt2==1000) cnt2<=10'b0;
    else if(cnt1==1000) cnt2<=cnt2+1'b1;
end

reg [5:0] cnt3;
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n) cnt3<=6'b0;
    else if(cnt3==25) cnt3<=6'b0;
    else if(cnt2==1000) cnt3<=cnt3+1'b1;
end
//-----------------show---------------
always@(posedge clk or negedge rst_n)
begin
     if(!rst_n) led_show<={26'b1,1'b0};   //这里的初始化只点亮第二个灯
     else if(cnt3==25) led_show<={led_show[25:0],led_show[26]};  
end


endmodule