4、通用偶数分频
以4分频为例:
module even_div
#(
parameter CNT_MAX = 3'd4,
parameter WIDE = 8'd12
)
( input wire clk,
input wire rst_n,
output reg clk_out
);
reg [WIDE-1:0] cnt;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
cnt <= 2'b0;
else if (cnt == (CNT_MAX>>1) - 1)
cnt <= 2'b0;
else
cnt <= cnt + 1'b1;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
clk_out <= 1'b0;
else if (cnt == (CNT_MAX>>1) - 1)
clk_out <= ~clk_out;
end
endmodule