LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY LED IS
GENERIC (LIMIT : INTEGER := 255);
PORT (
sys_clk : IN STD_LOGIC;
--sys_rst_n : OUT STD_LOGIC;
MY_LED : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
MY_KEY : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
BOARD_LED_RED : OUT STD_LOGIC;
BOARD_LED_GREEN : OUT STD_LOGIC;
BOARD_LED_BLUE : OUT STD_LOGIC
);
END ENTITY LED;
ARCHITECTURE BEV OF LED IS
SIGNAL timer_count1 : INTEGER := 0;
SIGNAL timer_count2 : INTEGER := 0;
SIGNAL buff : BIT_VECTOR(7 DOWNTO 0) := "11111110";
SIGNAL CLK_Counter : INTEGER := 0;
SIGNAL MY_CLK : STD_LOGIC := '0';
CONSTANT TIME_1 : INTEGER := 24000000; ---1s
CONSTANT TIME_2 : INTEGER := 12000000; ---0.5s
----------------------上升沿函数------------------------------
FUNCTION positive_edge(SIGNAL s : STD_LOGIC) RETURN BOOLEAN IS
BEGIN
RETURN(s'event AND s = '1');
END FUNCTION positive_edge;
----------------------下降沿函数------------------------------
FUNCTION falling_edge(SIGNAL s : STD_LOGIC) RETURN BOOLEAN IS
BEGIN
RETURN(s'event AND s = '0');
END FUNCTION falling_edge;
BEGIN
--本系统时钟为 24Mhz,一个机器周期为 1/24M s,也就是说每过 12000000 个时钟周期为 0.5s
CKK_Timer : PROCESS (sys_clk)
BEGIN
IF positive_edge(sys_clk) = TRUE THEN
CLK_Counter <= CLK_Counter + 1;
IF CLK_Counter = 24000000 THEN --计时1
MY_CLK <= NOT MY_CLK;
--MY_LED(0) <= NOT MY_LED(0);
CLK_Counter <= 0;
END IF;
END IF;
END PROCESS; -- CKK_Timer
TEST_CLK : PROCESS (MY_CLK) --2s脉冲
BEGIN
IF positive_edge(MY_CLK) THEN
MY_LED(7) <= NOT MY_LED(7);
END IF;
END PROCESS; -- TEST_CLK
D_flip_flop : PROCESS (MY_CLK)
BEGIN
IF positive_edge(MY_CLK) THEN
MY_LED(0) <= MY_KEY(0);
END IF;
END PROCESS; -- D_flip_flop
END ARCHITECTURE BEV;
VHDL D触发器
最新推荐文章于 2024-03-16 15:29:27 发布