library ieee;
use ieee.std_logic_1164.all;
entity a3 is
port(d,clk:in std_logic;
q:out std_logic);
end a3;
architecture b1 of a3 is
begin
process(d, clk)
begin
if clk'event and clk ='1' then
q<=d;
end if;
end process;
end b1;
use ieee.std_logic_1164.all;
entity a3 is
port(d,clk:in std_logic;
q:out std_logic);
end a3;
architecture b1 of a3 is
begin
process(d, clk)
begin
if clk'event and clk ='1' then
q<=d;
end if;
end process;
end b1;