Innovus tcl commands notes

Innovus tcl指令 笔记

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前言

为了更加方便使用Innovus来进行设计，整理我常用的tcl指令和流程。
以下包括：
如何使用命令行执行.tcl指令
如何导入.lef .v .def .sdc .lib文件
如何运行Placement
如何运行Pre-CTS / Post-CTS / Post-Route Timing Optimization
如何运行Global routing + Detailed routing
如何进行Design rule check

一、文件类型

1. .lef file
   用于定义technology node以及macro cell信息。
   具体格式可参考 LefDef5.7 LefDef5.8
2. .v file
   verilog文件，用于描述网表（netlist）信息。
3. .def file
   用于描述cell位置
   具体格式可参考 LefDef5.7 LefDef5.8
4. .sdc file
   timing constraint文件
   a set of .sdc file to define clock, condition, IO timing, path exception, etc.
5. .lib file
   timing library文件
   a group of library files from different process corners, operating voltages (for MSMV power domain)
   can include both timing .libs and signal integrity .cdb

二、Tcl指令

1. Innovus调用tcl文件

innouvs -no_gui -cpus <number/of/cpus> -files <path/to/tcl/file> -log <path/to/log(cmd, logv)/file>

2. 文件导入，design初始化

# Note that you should read technology library first
set init_lef_file {<path/to/lef/file1.lef> <path/to/lef/file2.lef>} # import lef file

set init_verilog <path/to/verilog/file.v> # import verilog file

# Another method to import verilog file
set design_netlisttype verilog
set init_verilog [list file1.v file2.v]
set init_design_set_top 1 # 0 means auto assign the top cell
set init_top_cell “top” # specify the top cell by yourself

set init_mmmc_file <path/to/mmmc/file.tcl> #import mmmc file for timing

init_design # initialize design

# Import def file
DefIn <path/to/def/file.def>

mmmc file以mmmc.tcl为例

上图为我们需要在mmmc file中所设置的内容。

# set the name of your .lib file (e.g. Lib6710_01.lib)
# You can create multiple library sets if you have multiple libraries
# such as fast, slow, and typ
# If you have multiple .lib files put them in a [list lib1 lib2] structure
create_library_set -name typical_lib -timing {!!your-lib-file!!.lib}
# Specify the .sdc timing constraint file to use
# This file comes from Synopsys synthesis. (e.g. design_struct.sdc)
create_constraint_mode -name typical_constraint -sdc_files {!!your-sdc-file!!.sdc}
#################################################################
# Below here you shouldn't have to change, unless you're doing
# something different than the basic EDI run...
#################################################################
# Create an RC_corner that has specific capacatance info.
create_rc_corner -name typical_rc …
# Define delay corners and analysis views.
create_delay_corner -name typical_corner -library_set {typical_lib} -rc_corner {typical_rc}
create_analysis_view -name typical_view -constraint_mode {typical_constraint} -delay_corner {typical_corner}
# Now define which analysis view to use for setup and for hold.
set_analysis_view -setup {typical_view} -hold {typical_view}

One sample mmmc.tcl

create_library_set -name MIN_TIMING -timing {./iccad_2015/superblue3/superblue3_Early.lib}
create_library_set -name MAX_TIMING -timing {./iccad_2015/superblue3/superblue3_Late.lib}
create_constraint_mode -name CONSTRAINTS -sdc_files ./iccad_2015/superblue3/superblue3.sdc
create_rc_corner -name RC_BEST -preRoute_res {1.0} -preRoute_cap {1.0} -preRoute_clkres {0.0} -preRoute_clkcap {0.0} -postRoute_res {1.0} -postRoute_cap {1.0} -postRoute_xcap {1.0} -postRoute_clkres {0.0} -postRoute_clkcap {0.0}
create_rc_corner -name RC_WORST -preRoute_res {1.0} -preRoute_cap {1.0} -preRoute_clkres {0.0} -preRoute_clkcap {0.0} -postRoute_res {1.0} -postRoute_cap {1.0} -postRoute_xcap {1.0} -postRoute_clkres {0.0} -postRoute_clkcap {0.0}
create_delay_corner -name MIN_DELAY -library_set {MIN_TIMING} -rc_corner {RC_WORST}
create_delay_corner -name MAX_DELAY -library_set {MAX_TIMING} -rc_corner {RC_BEST}
create_analysis_view -name BEST_CASE -constraint_mode {CONSTRAINTS} -delay_corner {MIN_DELAY}
create_analysis_view -name WORST_CASE -constraint_mode {CONSTRAINTS} -delay_corner {MAX_DELAY}
set_analysis_view -setup {WORST_CASE} -hold {BEST_CASE}

Placement

在physical design flow中placement分为global placement，legalization和detailed placement三个阶段。下图为Innovus placement stage对应的GUI。

setPlaceMode -timingDriven true -congEffort auto
placeDesign # Optional placeDesign switches: -inPlaceOpt or -prePlaceOpt

setPlaceMode -congEffort auto -timingDriven true -ignoreScan true
placeDesign

refinePlace的功能与legalization很像，目的都是使结果变为legal。但直接使用placeDesign便可以得到legal placement solution，并可以通过使用setPlaceMode来调整timing-driven和congestion-driven的力度。

Timing

在Innovus的理想flow中，会进行三次timing analysis和timing optimization。
分别为

• Pre-CTS (clock tree synthesis) – trial route after placing cells
• Post-CTS – clock tree should improve timing
• Post-Route – after completed routing

会被用于优化timing, SI, area, and power的操作：

• add/delete buffer
• resize gate
• restructure netlist
• remap logic
• swap pin
• move inst
• apply useful skew
• layer opt
• track opt

timeDesign: create trial route, extract delays, analyze timing, generate reports.
optDesign: resize gates, restructure netlist, add/delete buffers, swap pins, move instances.

Timing Analysis:

setAnalysisMode -analysisType onChipVariation -skew true -clockPropagation sdcControl # Only use for postRoute
timeDesign -preCTS -idealClock -numPaths 50 -prefix preCTS -outDir ${BASENAME}_reports/preCTS # preCTS can be modified to postCTS or postRoute

Timing Optimization:

setOptMode -yieldEffort none
setOptMode -effort high
setOptMode -maxDensity 0.95
setOptMode -fixDRC true
setOptMode -fixFanoutLoad true
setOptMode -optimizeFF true
setOptMode -simplifyNetlist false
setOptMode -holdTargetSlack 0.0
setOptMode -setupTargetSlack 0.0
clearClockDomains
setClockDomains -all
setOptMode -usefulSkew false
optDesign -preCTS -drv -outDir ${BASENAME}_reports/preCTSOptTiming

Routing

earlyGlobalRoute

Early Global Route (earlyGlobalRoute) is a quick global routing for estimating routing-related congestion and parasitic (resistance and capacitance) values. The Early Global Route results are also used for pin assignment when you commit partitions in hierarchical designs. Early Global Route does not guarantee DRC-clean routing results. Do not perform signal integrity analysis on a design that has been routed using Early Global Route, because these routes are only used to estimate parasitic values for timing analysis. Route designs with the NanoRoute router if you want to perform signal integrity analysis.

• You can set the global parameters for the Early Global Route program by using the setRouteMode command.
• The assignPtnPin command reports the number of guide pins from route guides and fixed pins.

earlyGlobalRoute -help
# Outputs a brief description that includes type and default information for each earlyGlobalRoute parameter.
# For a detailed description of the command and all of its parameters, use the man command:
man earlyGlobalRoute

globalRoute

This command is used to plan the interconnect by breaking the routing portion of the design into rectangles called global routing cells (gcells) and assigning the signal nets to the gcells. It will conduct global routing using Innovus.

detailRoute

This command is used to use the NanoRoute router to perform detailed routing on the entire design, an area of the design specified by the bounding box, or on selected nets. If you do not specify parameters, the router routes the entire design. If you specify both the bounding box and selected nets, the router routes only selected nets within the bounding box. You can perform detailed routing on specified area only if you are rerouting the design. If you have not already run detailed routing on the entire design, you cannot run detailed routing on a specified area.

detailRoute [-help] [-select] [<area>]

-help  Outputs  a brief description that includes the type and default information for each detailRoute parameter. For a detailed description of the command and all of its parameters, use the man command:
              man detailRoute
<area> Specifies the x and y coordinates of the bounding box area.
       Data_type: rect, optional
-select Routes selected nets. To select a net, use the selectNet command or click the net in the design display window.
        Tip: You can also specify setNanoRouteMode -routeSelectedNetOnly true to route the selected nets.
        Data_type: bool, optional

globalDetailRoute

globalDetailRoute uses the NanoRoute router to perform both global and detailed routing with one command. When you load a partially routed database, the router completes the routes.

globalDetailRoute [-help] [-select] [<area>]

<area> Specifies the coordinates  (x1 y1 x2 y2) of the bounding box area for detailed routing. The entire design is globally routed.
       Data_type: rect, optional
-help  Outputs  a  brief  description that includes the type and default information for each globalDetailRoute parameter. For a detailed description of the command and all of its parameters, use the man command: 
	   man globalDetailRoute
-select Routes selected nets. To select a net, use the selectNetcommand or click the net in the design display window.
        Tip: You can also specify setNanoRouteMode -routeSelectedNetOnly true to route the selected nets.
        Data_type: bool, optional

Note: If you have not already run detailed routing on the entire design, you cannot run detailed routing on a specified area.

routeDesign

routeDesign runs routing or postroute via or wire optimization using the NanoRoute router. If you specify this command without any arguments, it runs global and detailed routing.

routeDesign  [-help]  [-bump] [-highFrequency] [-selected] [-viaPillarOpt] [[[-clockEco ] [-globalDetail ] [-placementCheck | -noPlacementCheck ] [[ -trackOpt ] [-idealClock ]] [-viaOpt ] [-wireOpt ]] | [-passiveFill ]]

# For details, using 'man routeDesign'

Related setting tcl

在routing阶段的相关设置命令如下：

• setNanoRouteMode
• setRouteMode
• setAttribute

Reference

[1]https://www.eng.auburn.edu/~nelson/courses/elec5250_6250/slides/ASIC%20Layout_2%20%20Digital%20Innovus.pdf
[2] https://phdbreak99.github.io/blog/note/2017-04-01-innovus-training/

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总结

记录常用的tcl指令 To Be Continue…