Innovus tcl commands notes

Innovus tcl指令 笔记

---

前言

为了更加方便使用Innovus来进行设计，整理我常用的tcl指令和流程。
以下包括：
如何使用命令行执行.tcl指令
如何导入.lef .v .def .sdc .lib文件
如何运行Placement
如何运行Pre-CTS / Post-CTS / Post-Route Timing Optimization
如何运行Global routing + Detailed routing
如何进行Design rule check

一、文件类型

1. .lef file
   用于定义technology node以及macro cell信息。
   具体格式可参考 LefDef5.7 LefDef5.8
2. .v file
   verilog文件，用于描述网表（netlist）信息。
3. .def file
   用于描述cell位置
   具体格式可参考 LefDef5.7 LefDef5.8
4. .sdc file
   timing constraint文件
   a set of .sdc file to define clock, condition, IO timing, path exception, etc.
5. .lib file
   timing library文件
   a group of library files from different process corners, operating voltages (for MSMV power domain)
   can include both timing .libs and signal integrity .cdb

二、Tcl指令

1. Innovus调用tcl文件

innouvs -no_gui -cpus <number/of/cpus> -files <path/to/tcl/file> -log <path/to/log(cmd, logv)/file>

2. 文件导入，design初始化

# Note that you should read technology library first
set init_lef_file {
   <path/to/lef/file1.lef> <path/to/lef/file2.lef>} # import lef file

set init_verilog <path/to/verilog/file.v> # import verilog file

# Another method to import verilog file
set design_netlisttype verilog
set init_verilog [list file1.v file2.v]
set init_design_set_top 1 # 0 means auto assign the top cell
set init_top_cell “top” # specify the top cell by yourself

set init_mmmc_file <path/to/mmmc/file.tcl> #import mmmc file for timing

init_design # initialize design

# Import def file
DefIn <path/to/def/file.def>

mmmc file以mmmc.tcl为例

上图为我们需要在mmmc file中所设置的内容。

# set the name of your .lib file (e.g. Lib6710_01.lib)
# You can create multiple library sets if you have multiple libraries
# such as fast, slow, and typ
# If you have multiple .lib files put them in a [list lib1 lib2] structure
create_library_set -name typical_lib -timing {
   !!your-lib-file!!