system verilog assert 延时变量

##variable：

• 正常情况写 ##5，##后跟常数数字
• 需要用到变量的延时可以这么写

property time_wait;
	int cnt=limit;
    @(posedge clk) $rose(a) |-> (cnt>0, cnt--)[*] ##1 cnt==0;
endproperty

assert property (time_wait);

//直接写 ##variable,报错：
// ##后需要跟常量
The use of a non-constant expression is not allowed in properties, sequences and assertions for cases such as delay and repetition ranges.
Please replace the offending expression by an elaboration-time constant.

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