仿真测试 timescale 1 ps/ 1 ps define clock_period 20 module uart_ram_vlg_tst();reg clk; reg rst_n; wire Rx232_rx; wire key_in; wire Rs232_tx; wire [2:0] baud_set; reg send_en; reg press; reg [7:
仿真测试
timescale 1 ps/ 1 ps define clock_period 20
module uart_ram_vlg_tst();
reg clk;
reg rst_n;
wire Rx232_rx;
wire key_in;
wire Rs232_tx;
wire [2:0] baud_set;
reg send_en;
reg press;
reg [7:0] data_Byte_t;
wire Tx_done;
assign band_set=3’d0;
// port map - connection between master ports and signals/registers
uart_tx uart_tx1(
.Rs232_tx(Rs232_rx),
.Tx_done(Tx_done),
.Uart_state(),
.baud_set(3’d0),
.clk(clk),
.data_Byte(data_Byte_t),
.rst_n(rst_n),
.send_en(send_en)
);
key_model key_model1(
.press(press),
.key(key_in)
);
uar
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