Simulation and Synthesis Techniques for AsynchronousFIFO Design

Clifford E. Cummings, Sunburst Design, Inc.cliffc@sunburst-design.com

5.0 Handling full & empty conditions

Exactly how FIFO full and FIFO empty are implemented is design-dependent.
The FIFO design in this paper assumes that the empty flag will be generated in the read-clock domain to insure that the empty flag is detected immediately when the FIFO buffer is empty, that is, the instant that the read pointer catches up to the write pointer (including the pointer MSBs).
//标志位相同
The FIFO design in this paper assumes that the full flag will be generated in the write-clock domain to insure that the full flag is detected immediately when the FIFO buffer is full, that is, the instant that the write pointer catches upto the read pointer (except for different pointer MSBs).
//标志位不同

5.1 Generating empty

As shown in Figure 1, the FIFO is empty when the read pointer and the synchronized write pointer are equal.
The empty comparison is simple to do. Pointers that are one bit larger than needed to address the FIFO memory buffer are used. If the extra bits of both pointers (the MSBs of the pointers) are equal, the pointers have wrapped the same number of times and if the rest of the read pointer equals the synchronized write pointer, the FIFO is empty.
//加入标志位 后的地址位完全相同 空
The Gray code write pointer must be synchronized into the read-clock domain through a pair of synchronizer registers found in the sync_w2r module. Since only one bit changes at a time using a Gray code pointer, there is no problem synchronizing multi-bit transitions between clock domains.
｜ 写addr 的Gray 必须cdc 到 read_ck domains //2-DFF
In order to efficiently register the rempty output, the synchronized write pointer is actually compared against the rgraynext (the next Gray code that will be registered into the rptr). The empty value testing and the accompanying sequential always block has been extracted from the rptr_empty.v code of Example 6 and isshown below:
//读的addr 比较的是下一个写入地址的gray_addr 实际产生的是empty_flow

5.2 Generating full

5.2 Generating full
Since the full flag is generated in the write-clock domain by running a comparison between the write and read pointers, one safe technique for doing FIFO design requires that the read pointer be synchronized into the write clock domain before doing pointer comparison.
｜
The full comparison is not as simple to do as the empty comparison. Pointers that are one bit larger than needed to address the FIFO memory buffer are still used for the comparison, but simply using Gray code counters with an extra bit to do the comparison is not valid to determine the full condition. The problem is that a Gray code is a symmetric code except for the MSBs.
｜ //由于gray对称 full的产生不可直接比较addr 如： rd_addr = 0_001 wr_addr = 1_001 不为full
Consider the example shown in Figure 6 of an 8-deep FIFO. In this example, a 3-bit Gray code pointer is used to address memory and an extra bit (the MSB of a 4-bit Gray code) is added to test for full and empty conditions. If theFIFO is allowed to fill the first seven locations (words 0-6) and then if the FIFO is emptied by reading back the same seven words, both pointers will be equal and will point to address Gray-7 (the FIFO is empty). On the next write operation, the write pointer will increment the 4-bit Gray code pointer (remember, only the 3 LSBs are being used to address memory), making the MSBs different on the 4-bit pointers but the rest of the write pointer bits will match the read pointer bits, so the FIFO full flag would be asserted. This is wrong! Not only is the FIFO not full,but the 3 LSBs did not change, which means that the addressed memory location will over-write the last FIFO memory location that was written. This too is wrong!