weixuweixu-CSDN博客

原创 How to optimize Priority encoder in FPGA

optimize a priority Mux encoder from 12 logic levels to 5

2022-06-09 06:13:09 163

原创 Some SystemVerliog functions

package global_functions_pkg;function int log2ceil(input int unsigned a); int i; int unsigned p2i; //int unsigned p2i = 1; begin p2i = 1; //for(i=0, p2i=1; p2i<a; i++) for(i=0; p2i<a; i++) p2i<&l.

2022-04-14 08:17:52 154

原创 Embedded C Note

1. gcc2. Macro #define ABC(5+3) #defien ABC(x) 5+(x)3. Singed: MSB is sign bit. 1 is negative

2021-07-15 15:11:45 113

原创 COMPUTER ARCH INTERVIEW QUESTIONS

1. Memory Hierarchyregister --> cache(normally integrated in CPU) --> memory(DRAM) --> disk --> tape2. cache hit: Data found in cache cache miss: not found in cache, Processor loads data from memory. This result in extra delay, calle...

2021-07-08 16:48:46 144

原创 SRAM and RLDRAM

SRAM:Static RAM (SRAM) consists of flip-flops, a bistable circuit composed offourto six transistors. Once a flip-flop stores a bit, it keeps that value until the opposite value is stored in it.SRAM CELL: Vertical: bit line. Horizontal: word line...

2021-06-28 11:54:05 452

原创 FPGA TIMING CONSTRIANT(.sdc)

WHY WE NEED TIMING CONSTRAINT:RELAX TIMING REQUIREMENTSNomally set on "not real critical path"Some logic paths needmore than 1 cycle to propogate to next squential cellDefinitionsetup time:the amount of time the data at the synchronous input (...

2021-06-05 01:23:45 1126

原创 vivado,从rtl到bitstream以及如何用JTAG进行硬件测试

There are three stages in vivado from RTL to Bitstream（从逻辑设计到bitstream的三个阶段）综合: 这个步骤将会把你的硬件语言代码转换成netlist。In Synthesizeprocess, RTL design (verilog/VHDL) is compiled and translated into netlist implementation：这个步骤会把你生成的netlist投射到你选择型号的FPGA上, 并且能生成电路时间报.

2020-09-17 03:07:34 2214 1

原创 Quartus Signal Tap II Debugging

working environment:LinuxStepsOpen RTL project:open quartus under Linux:quartusopen project file (file that ends with .qpt)Signal tap IITool -> singal Tap IIAdding clocksignal configuration -> name:clock -> filter: Signal Tap II Pre-sy

2020-07-22 03:06:40 212

原创用Git远程工作的几种基本使用方法，下载DOWNLOAD，覆盖OVERWRITE，上传UPLOAD。

如何使用git1. How to connect to remote branch using git如何绑定远程文件库到本地step1：下载git(DOWNLOAD GIT)sudo apt-add-repository ppa:git-core/ppasudo apt-get updatesudo apt-get install gitstep2：初始化git（Configure Git）认证你是working branch的作者在你的终端输入：git config --globa

2020-06-23 05:06:28 715

原创 How to send packets using IxEplorer

IxEplorer can be used to send and recieve customized data or send imported ".enc" data as stream.IxEplorer 这个软件可以用来发送和接收自定义数据包或者导入“enc”文件发送。Part 1: Setting your own streamStep 1.The device I ...

2020-03-31 04:42:52 198

原创 Using genvar to build delay block(Verilog genvar的使用)

Genvar is widly use when we want to instantiate lots of gates/modules. In this case, we use “genvar” to generate a delay block that usesregisters in serial.module delay(q,d,clock);output [WIDTH-1...

2019-05-08 03:00:11 458

原创 Use FSMD to interpret high level c++ code (用带有数据通道的有限状态机来编写c++方程)

Finite state machine with data path:FSMD has two parts, FSM and Datapath. It's a more flexible mechanism to control data in different stage than FSM. In a standard FSMA, FSM is used to change the st...

2019-03-19 04:13:38 331

原创 Embedded System-LAB1-PART3(DEVICE DRIVER AND ITS OPERATIONS)

Part 3. Base Module for memory operationsRequirement:This module is basically a memory management service that will allocate, read, write, and delete bytes of memory at the request of a user applic...

2019-01-16 13:02:53 418

原创 Embedded System-LAB1-PART1-PART2(loadable module and passing argument)

IntroductionI took "Mobile & embedded system" before and decided to write a summary of the labs I've done in that course. TheArm-based microcontroller I used is called Beaglebone Black.There ...

2018-12-17 13:28:50 203

原创 Asynchronous FIFO with gray code（异步FIFO verilog设计理念）

代码来自asic world 和paper“ Simulation and Synthesis Techniques for Asynchronous FIFO Design”，文章解说均为自己的理解，如果有错误欢迎纠正～What is FIFO?FIFO 是一个满足“先进先出”的储存数据的结构，如果我以“A->B->C”的顺序存入数据，由于我先存入的C,那么我先读取的内...

2018-09-23 10:54:09 9111

转载 Clock divider

1. Odd integer division(not 50% duty cycle)Design Moore machine (take "7" as example)2. Odd integer division with 50% duty cycleConceptually, the easiest way to create an odd divider with a 50...

2018-07-28 10:06:17 2836

原创 FPGA vs ASIC

ASIC(Application Specific Integrated Circuit) is atype of IC that is designed with a certain purpose, the functionof ASIC is fixed after production.Advantages:High performance, high speed, low p...

2018-07-20 06:18:30 779

转载 SystemVerilog note (3)

SystemVerilog TestBench Example - ADDERPart 1 TransactionFields required to generate the stimulus are declared in the transaction class. Transaction class can also be used as the placeholder ...

2018-07-19 12:51:00 301

转载 SystemVerilog note(2)

SV - OOP Concepts (object-oriented programming)Reference:http://www.verificationguide.com/p/systemverilog-classes_23.htmlclassA class is a description of some group of things that have somethi...

2018-07-17 13:11:37 218

原创 Verilog practice

Q1: write Verilog code to generate below waveform: Q2: write Verilog code to generate below waveform:Since there is one delay after the rising edge of data in, three delays after the negedge...

2018-07-07 08:51:04 350

转载 SytemVerilog note (1)

-----------------------Occasional Updates-----------------------I want to share some notes about SystemVerilog, I'm a beginner at this.Part1 Data Type:bit : unsigned; byte: signed.Part2 Task...

2018-07-07 00:58:21 252

原创 Use EMIO and MIO to control Pmod GPIOS on zedboard by vivado and SDK (Zedboard)

AXI GPIOs can be set to either read or write:Step one, create block design in vivado:

2018-07-06 15:31:53 656

原创 Vivado block design with both AXI GPIO and custom IP (ZEDBOARD)

Custom IP: First step: Create a block design ->Tools -> Create and Package New IP -> Create new AXI4 Peripheral -> set a name for your new IP.(This IP will be saved under a file named "ip_...

2018-07-06 12:45:41 1046

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