DUT这边的Interface定义:
interface aa_bb_if();
logic a2b_rsp_vld ;
logic [ 1:0] a2b_rsp_ts ;
modport a2b(
output a2b_rsp_vld ,
output a2b_rsp_ts
);
modport b2a(
input a2b_rsp_vld ,
input a2b_rsp_ts
);
endinterface
验证环境这边对应的Interface定义:
interface dv_aa2bb_interface (input bit clk, input bit rst_n);
parameter setup_time = 0.01;//ns
parameter hold_time = 0.01;//ns
logic [ 0:0] aa_bb_rsp_vld;
logic [ 1:0] aa_bb_rsp_ts; //
clocking driver_cb @(posedge clk);
default input #setup_time output #hold_time;
output aa_bb_rsp_vld;
output aa_bb_rsp_ts;
endclocking: driver_cb
clocking monitor_cb @(posedge clk);
default input #setup_time output #hold_time;
input aa_bb_rsp_vld;
input aa_bb_rsp_ts;
endclocking: monitor_cb
modport drv_cb(clocking driver_cb);
modport mon_cb(clocking monitor_cb);
`ifdef ASSERT_ON
//----------------add your assertion of interface here -----------------//
// property err_valid;
// @(posedge clk) $rose(err) |=> $fell(valid);
// endproperty
// assert_err_valid: assert property(err_valid);
`endif
endinterface: dv_aa2bb_interface
top_tb层的例化连接:
module top_tb();
//......
aa_bb_if aa2bb_if ;
XX_DUT U_DUT(
.clk (clk),
.u_aa_bb_if (aa2bb_if )
);
`include "top_if.sv"
endmodule
top_if的连接:
dv_aa2bb_interface u_dv_aa_bb_interface[1] (.clk(`TOP_TB.clk),.rst_n(`TOP_TB.rst_n));
//这里还有一个关键步骤:interface的句柄赋值给 virtual interface并set给对应组件;
virtual dv_aa2bb_interface vir_dv_aa_bb_interface[1];
vir_dv_aa_bb_interface = u_dv_aa_bb_interface;
foreach(vir_dv_aa_bb_interface[i])begin
uvm_config_db #(virtual dv_aa2bb_interface )::set(null, $sformatf("uvm_test_top.env.m_aa_bb_agent[%0d]*",i), "bus",vir_dv_aa_bb_interface[i]);
end
//assign:右边是驱动源
assign `TOP_TB.aa2bb_if.a2b_rsp_vld = u_dv_aa_bb_interface[0].aa_bb_rsp_vld ;
assign `TOP_TB.aa2bb_if.a2b_rsp_ts = u_dv_aa_bb_interface[0].aa_bb_rsp_ts ;
还有一种场景是环境代码都是直接放到pakage里面:
1)interface定义同上;
2)interface文件在filelist中,要放到声明interface文件的前面编译;
3)top层:
4)refm层: