fifo.v
module fifo( input rstn , input clk , input wr_en , input rd_en , input [7:0] wr_dat , output reg [7:0] rd_dat , output empty , output full ); reg [7:0] mem [0:255]; reg [8:0] wr_addr; reg [8:0] rd_addr; always @(posedge clk or negedge rstn) begin if(!rstn) wr_addr <= 9'd0; else if(wr_en && ~full) wr_addr <= wr_addr + 9'd1; end always @(posedge clk or negedge rstn) begin if(!rstn) rd_addr <= 9'd0; else if(rd_en && ~empty) rd_addr <= rd_addr + 9'd1; end assign full = (wr_addr[8]^rd_addr[8])&(wr_addr[7:0] == rd_addr[7:0]); assign empty = (wr_addr==rd_addr); integer i; always @(posedge clk or negedge rstn) begin if(!rstn) begin for(i=0;i<=255;i=i+1) mem[i] <= 8'd0; end else if(wr_en && ~full) mem[wr_addr] <= wr_dat; end always @(posedge clk or negedge rstn) begin if(!rstn) rd_dat <= 8'd0; else if(rd_en && ~empty) rd_dat <= mem[rd_addr]; end endmodule