该博客介绍了如何用Verilog设计一个32位边沿捕获寄存器，该寄存器在输入信号从1变为0时捕捉变化，并在重置信号为高时将输出设为0。当下降沿检测和重置事件同时发生时，重置优先级更高。文中提供了正确代码并分析了初稿中的错误，指出单个触发器即可完成边沿检测。
题目：
For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. "Capture" means that the output will remain 1 until the register is reset (synchronous reset).
Each output bit behaves like a SR flip-flop: The output bit should be set (to 1) the cycle after a 1 to 0 transition occurs. The output bit should be reset (to 0) at the positive clock edge when reset is high. If both of the above events occur at the same time, reset has precedence. In the last 4 cycles of the example waveform below, the 'reset' event occurs one cycle earlier than the 'set' event, so there is no conflict here.
In the example waveform below, reset, in[1] and out[1] are shown again separately for clarity.
题目理解：
输入为32位的数据，检测每一位的下降沿，如果检测到下降沿
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