异步输入上升沿检测

module cy4(
       input sig_a,
       input clk,
       input rstb,
       output sig_a_posedge
       );
reg sig_a_d1,sig_a_d2,sig_a_d3;
always @(posedge clk or negedge rstb)
  if(!rstb) 
  begin
  sig_a_d1 <= 1'b0;
  sig_a_d2 <= 1'b0;
  sig_a_d3 <= 1'b0;
  end
  else 
  begin 
  sig_