级联BCD计数器设计与仿真(模10)

//级联BCD计数器设计与仿真
module BCD(Clk,Rst_n,Cin,Cout,q);
input Cin;
input Clk;
input Rst_n;
output Cout;
output[3:0]q;
reg[3:0]cnt;

always@(posedge Clk or negedge Rst_n)	
if(!Rst_n) cnt <= 1'b0;
else if(Cin == 1)begin
if(cnt == 4'd9)
cnt <= 4'b0;
else cnt <= cnt + 1'b1;
end
else cnt <= cnt;
module BCD_C(Cin,Clk,Rst_n,Cout,q);
input Cin;
input Clk;
input Rst_n;

output Cout;
output [11:0]q;

wire Cout0;
wire Cout1;
wire[3:0]q0,q1,q2;

assign q ={q2,q1,q0};

BCD BCD_0(
     .Cin(Cin),
	 .Clk(Clk),
	 .Rst_n(Rst_n),
	 .Cout(Cout0),
	 .q(q0)
	 );
BCD BCD_1(
     .Cin(Cout0),
	 .Clk(Clk),
	 .Rst_n(Rst_n),
	 .Cout(Cout1),
	 .q(q1)
	 );
BCD BCD_2(
     .Cin(Cout1),
	 .Clk(Clk),
	 .Rst_n(Rst_n),
	 .Cout(Cout),
	 .q(q2)
	 );
endmodule



assign Cout = (Cin == 1&&cnt == 4'd9);

assign q = cnt;
endmodule

测试脚本代码

`timescale 1 ns/ 1 ps
`define clock_period 20
module BCD_C_vlg_tst();
reg Cin;
reg Clk;
reg Rst_n;                                               
wire Cout;
wire [11:0]q;
                          
BCD_C i1 (  
	.Cin(Cin),
	.Clk(Clk),
	.Cout(Cout),
	.Rst_n(Rst_n),
	.q(q)
);
initial Clk= 1;
always #(`clock_period/2)Clk = ~Clk;
initial                                               
begin 
Rst_n = 1'b0;
Cin = 1'b0;
#(`clock_period*200);
Rst_n = 1'b1; 
#(`clock_period*20);                                                
Cin = 1'b1;
#(`clock_period*5000);
$stop;
end                                                        
endmodule