模10的BCD码计数器

module cy4(CLK,Rst_n,Cin,Cout,q);
input CLK;
input Rst_n;
input Cin;
output reg Cout;
output q;
wire [3:0]q;
reg[3:0] cnt;


always @(posedge CLK or negedge Rst_n)
if(!Rst_n)
cnt <= 4'd0;
else if(Cin == 1'b1)begin
if(cnt == 4'd9)
  cnt <= 4'd0;
else cnt <= cnt + 1'b1;
end
else
    cnt <= cnt;
	
always @(posedge CLK or negedge Rst_n)
if(!Rst_n) Cout <= 1'b0;
else if(Cin == 1'b1 && cnt == 4'd9)
         Cout <= 1'b1;
else Cout <= 1'b0;

assign q = cnt;
endmodule

仿真代码

`timescale 1 ns/ 1 ps
`define clock_period 20
module cy4_vlg_tst();

reg CLK;
reg Cin;
reg Rst_n;                                           
wire Cout;
wire [3:0]q;                      
cy4 i1 (  
	.CLK(CLK),
	.Cin(Cin),
	.Cout(Cout),
	.Rst_n(Rst_n),
	.q(q)
);

initial CLK = 1'b1; 
always #(`clock_period/2)CLK =