共阴极的七段显示译码器的代码

module cy4(input LE,BL,LT,//输入端口声明
           input D3,D2,D1,D0,//输入端口声明
           output reg a,b,c,d,e,f,g//输出端口及变量的数据类型声明
           );
always @(*)
begin
  if(LT == 1) {a,b,c,d,e,f,g} = 7'b111_1111;//让显示器的7段都发光,显示8
  else if(BL == 1) {a,b,c,d,e,f,g} = 7'b000_0000;//让显示器的7段都熄灭,显示0
  else if(LE == 1) {a,b,c,d,e,f,g} = {a,b,c,d,e,f,g};//锁存显示
  else
    case({D3,D2,D1,D0})//根据输入的8421BCD码,实现显示译码器的功能
    4'd0: {a,b,c,d,e,f,g} <= 7'b111_1110;
    4'd1: {a,b,c,d,e,f,g} <= 7'b011_0000;
    4'd2: {a,b,c,d,e,f,g} <= 7'b110_1101;
    4'd3: {a,b,c,d,e,f,g} <= 7'b111_1001;
    4'd4: {a,b,c,d,e,f,g} <= 7'b011_0011;
    4'd5: {a,b,c,d,e,f,g} <= 7'b101_1011;
    4'd6: {a,b,c,d,e,f,g} <= 7'b001_1111;
    4'd7: {a,b,c,d,e,f,g} <= 7'b111_0000;
    4'd8: {a,b,c,d,e,f,g} <= 7'b111_1111;
    4'd9: {a,b,c,d,e,f,g} <= 7'b111_1011;
    default: {a,b,c,d,e,f,g} <= 7'b000_0000;//非8421BCD码输入时,不显示
    endcase
end
endmodule