FPGA-verilog-写数字钟

1. 硬件平台

   Cyclone IV 和6个数码管

2. top level

module num_show(
	input clk,rst,
	output wire oclk,
	output  [7:0]num_out,
	output  [7:0]n_oled,
	output  [5:0]Cs_out,
	output wire clk_1M
);

   wire CLK_1M	;
	pll	pll_inst (
		.inclk0 ( clk ),
		.c0 ( CLK_1M )
		);
		
	flow_led	flow_led(
	.nclk(clk),.nrst(rst),
	.out_clk(oclk),
	.oled(n_oled)
);
		
	num_clock num_clock(
		.kclk(CLK_1M),.krst(rst),
		.knum_out(num_out),
		.kCs_out(Cs_out)
);
endmodule

2. 计时模块

module num_clock(
		input kclk,krst,
		output reg [7:0]knum_out,
		output reg [5:0]kCs_out
);
reg [20:0]count;
reg [3:0] s_num;
reg [3:0] s1_num;
reg [3:0] m_num;
reg [3:0] m1_num;
reg [3:0] h_num;
reg [3:0] h1_num;
reg [2:0] out_select;
parameter data = 20'd1000000;
//数码管
parameter _0 = 8'b0011_1111,
			 _1 = 8'b0000_0110,
			 _2 = 8'b0101_1011,
			 _3 = 8'b0100_1111, 
			 _4 = 8'b0110_0110,
			 _5 = 8'b0110_1101,
			 _6 = 8'b0111_1101,
			 _7 = 8'b0000_0111,
			 _8 = 8'b0111_1111,
			 _9 = 8'b0110_1111;
//from right left
parameter num_1 = 6'b11_1110,
			 num_2 = 6'b11_1101,
			 num_3 = 6'b11_1011,
			 num_4 = 6'b11_0111,
	       num_5 = 6'b10_1111,
			 num_6 = 6'b01_1111;
function [7:0]dataout;
input [3:0] in_data;
reg [7:0]out_data;
	begin
		case (in_data)
		4'd0:  out_data = _0;
		4'd1:  out_data = _1;
		4'd2:  out_data = _2;
		4'd3:  out_data = _3;
		4'd4:  out_data = _4;
		4'd5:  out_data = _5;
		4'd6:  out_data = _6;
		4'd7:  out_data = _7;
		4'd8:  out_data = _8;
		4'd9:  out_data = _9;
		default: out_data = 8'b1111_1111;	
		endcase
		dataout  = out_data;
	end
endfunction
always @(posedge kclk or negedge krst)
begin 
	if(!krst)
		begin
			kCs_out = num_1;
			out_select <= 1'b1;
			knum_out <= _0;
			count <= 0;
			s_num <= 0;
			s1_num <= 0; 
			m_num <= 0;
			m1_num <= 0; 
			h_num <= 0;
			h1_num <= 0; 
		end
	else
		begin
			count <= count + 1'b1;					   
				//计时
				if (count==data)
					begin
						count <= 0;
						//second
						s_num = s_num +1'b1;
						if (s_num == 4'b1010)
							begin
								s_num = 0;								
								s1_num = s1_num+ 1'b1;
								if(s1_num==4'b0110)
									begin								
										s_num = 0;
										s1_num = 0;
										m_num = m_num +1'b1;   //mini
										if (m_num == 4'b1010)
											begin 
												m_num = 0;								
												m1_num = m1_num+ 1'b1;
												if(m1_num==4'b0110)
												begin
													m_num = 0;
													m1_num = 0;
													h_num = h_num +1'b1;   //hour
												if (h_num == 4'b1010)
													begin 
														h_num = 0;								
														h1_num = h1_num+ 1'b1;
													end
												if(h1_num==4'b0010 && h_num == 4'b0100)   //24
														begin
															h_num = 0;
															h1_num = 0;													
														end
												end
											end										
									end								
							end																				
					 end
			//second
				//显示刷新率大于20HZ
			if(count % 20'd2500==0)				
				begin
					out_select=out_select+1'b1;
					if(out_select==3'b111)
						out_select=1'b1;
						
						case(out_select)
							3'b001:
									begin
										kCs_out = num_1;
										knum_out = dataout(s_num);
									end
							3'b010:
									begin
										kCs_out = num_2;
										knum_out = dataout(s1_num);
									end
							3'b011:
									begin
										kCs_out = num_3;
										knum_out = dataout(m_num);
									end
							3'b100:
									begin
										kCs_out = num_4;
										knum_out = dataout(m1_num);
									end
							3'b101:
									begin
										kCs_out = num_5;
										knum_out = dataout(h_num);
									end
							3'b110:
									begin
										kCs_out = num_6;
										knum_out = dataout(h1_num);
									end
							default: kCs_out = 6'b11_1111;	
						endcase
					
				end						
		end
end
endmodule
	

    
实验代码可根据不同的硬件平台自行修改。