FPGA开发--生成一幅分辨率为640*512的灰度图

生成一幅640*512的灰度图，灰度值16bit可调，行消隐可调，场消隐可调。

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2023/09/14 13:57:58
// Design Name: 
// Module Name: cmos_fake_img_gen
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module cmos_fake_img_gen(
	input clk,
	input rst_n,
	output cmos_vsync,
	output cmos_href,
	output cmos_pclk,
	output cmos_pvalid,
	output [13:0]cmos_pdata
    );
	
	parameter IMG_WIDTH = 640;
	parameter IMG_HIGHT = 512;
	// parameter VSYNC_BLANK = 50000;
	// parameter HREF_BLANK = 3000;
	parameter VSYNC_BLANK = 5000;
	parameter HREF_BLANK = 300;	
	
	parameter TEST_VALUE = 10;
	
	reg [7:0]st;
	reg [31:0]cnt;
	reg [15:0]pix_cnt;
	reg [15:0]line_cnt;
	reg vsync;
	reg href;
	reg pvalid;
	reg [15:0]pdata;
	reg [15:0]value;
	reg [15:0]frame_cnt;
	
	
	always@(posedge clk or negedge rst_n)begin
		if(rst_n == 1'b0)begin
			st<=8'd0;
			cnt<=32'd0;
			pix_cnt<=16'd0;
			line_cnt<=16'd0;
			vsync<=1'b0;
			href<=1'b0;
			pvalid<=1'b0;
			pdata<=16'd0;
			value<=TEST_VALUE;
			frame_cnt<=16'd0;
		end
		else begin
			case(st)
/*			
			8'd100:begin
				if(cnt < 32'd5_000_000)begin
					cnt<=cnt+1'b1;
					st<=8'd100;
				end
				else begin
					cnt<=32'd0;
					st<=8'd0;
				end			
			end
*/
			8'd0:begin
				if(cnt < VSYNC_BLANK)begin
					cnt<=cnt+1'b1;
					st<=8'd0;
				end
				else begin
					cnt<=32'd0;
					st<=8'd1;
					vsync<=1'b1;
					frame_cnt<=frame_cnt+1'b1;
				end
			end
			8'd1:begin
				if(cnt < HREF_BLANK)begin
					cnt<=cnt+1'b1;
					st<=8'd1;
				end
				else begin
					cnt<=32'd0;
					st<=8'd2;
					href<=1'b1;	
				end
			end
			8'd2:begin
				if(pix_cnt < IMG_WIDTH)begin
					pix_cnt<=pix_cnt+1'b1;
					pvalid<=1'b1;
					pdata<=value;
				end
				else begin
					if(line_cnt < IMG_HIGHT - 1)begin
						pix_cnt<=16'd0;
						pvalid<=1'b0;
						pdata<=16'd0;
						value<=value+16'd10;
						line_cnt<=line_cnt+1'b1;
						href<=1'b0;
						st<=8'd1;
					end
					else begin
						pix_cnt<=16'd0;
						pvalid<=1'b0;
						pdata<=16'd0;
//						value<=TEST_VALUE+frame_cnt;
						value<=TEST_VALUE;
						line_cnt<=16'd0;
						href<=1'b0;
						vsync<=1'b0;
						st<=8'd0;
					end
				end
			end			
			default: ;
			endcase
		end
	end
	
	assign cmos_vsync 	= vsync;
	assign cmos_href 	= href;
	assign cmos_pclk 	= clk;
	assign cmos_pvalid 	= pvalid;
	assign cmos_pdata 	= pdata[13:0];
	
endmodule