HDLbits 刷题 -- Mux9to1v

Create a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses b, etc. For the unused cases (sel=9 to 15), set all output bits to '1'.

Expected solution length: Around 15 lines.

译：

        创建一个16位宽的9对1多路复用器。Sel =0选择a, Sel =1选择b，等等。对于未使用的情况(sel=9到15)，将所有输出位设置为'1'。

预期解决方案长度:大约15行。

个人解法：

module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );
    always@(*)begin
        case(sel)
          4'b0000: out = a;
          4'b0001: out = b;
          4'b0010: out = c;
          4'b0011: out = d;
          4'b0100: out = e;
          4'b0101: out = f;
          4'b0110: out = g;
          4'b0111: out = h;
          4'b1000: out = i;
          default : out = 16'hffff;   
        endcase
    end  
        
endmodule

官方解法：

module top_module (
	input [15:0] a,
	input [15:0] b,
	input [15:0] c,
	input [15:0] d,
	input [15:0] e,
	input [15:0] f,
	input [15:0] g,
	input [15:0] h,
	input [15:0] i,
	input [3:0] sel,
	output logic [15:0] out
);

	// Case statements can only be used inside procedural blocks (always block)
	// This is a combinational circuit, so use a combinational always @(*) block.
	always @(*) begin
		out = '1;		// '1 is a special literal syntax for a number with all bits set to 1.
						// '0, 'x, and 'z are also valid.
						// I prefer to assign a default value to 'out' instead of using a
						// default case.
		case (sel)
			4'h0: out = a;
			4'h1: out = b;
			4'h2: out = c;
			4'h3: out = d;
			4'h4: out = e;
			4'h5: out = f;
			4'h6: out = g;
			4'h7: out = h;
			4'h8: out = i;
		endcase
	end
	
endmodule

运行结果：