`timescale 1ns / 1ps
//
module serial2paraller(
input clk,
input rst_n,
input d,
input en,
output wire [7:0] q
);
reg [11:0]cnt;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
cnt = 'd0;
end
else if(en)begin
if(cnt == 'd63)begin
cnt <= 'd0;
end
else begin
cnt <= cnt + 1'd1;
end
end
else begin
cnt <= 'd0;
end
end
reg [7:0] data;//寄存器
reg [7:0] cn;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
data <= 8'd0;
cn <= 'd0;
end
else if(en)begin
if(cnt == 'd35)begin
data <= {data[6:0],d};
cn <= cn + 'd1;
end
end
end
reg [7:0] q_buf;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
cn <= 'd0;
end
else if(en)begin
if(cnt == 'd35)begin
if(cn == 'd7) begin
cn <= 'd0;
q_buf <= data;
end
else begin
cn <= cn + 'd1;
q_buf <= 'd0;
end
end
end
end
assign q = q_buf ;
//===================================================ram===================================
endmodule