module mul_timequest#( parameter DIN_W = 8, parameter DOU_W = 32 ) ( input clk, input rst_n, input vld_in, input [DIN_W-1'b1:0] a, input [DIN_W-1'b1:0] b, input [DIN_W-1'b1:0] c, input [DIN_W-1'b1:0] d, output reg [DOU_W-1'b1:0] dout, output reg vld_out ); reg [DOU_W-1'b1:0] dout1; reg [DOU_W-1'b1:0] dout2; reg [DOU_W-1'b1:0] a_ff0; reg [DOU_W-1'b1:0] b_ff0; reg [DOU_W-1'b1:0] c_ff0; reg [DOU_W-1'b1:0] d_ff0; always@(posedge clk or negedge rst_n)begin if(!rst_n)begin a_ff0 <= 0; b_ff0 <= 0; c_ff0 <= 0; d_ff0 <= 0; end else begin a_ff0 <= a; b_ff0 <= b; c_ff0 <= c; d_ff0 <= d; end end always@(posedge clk or negedge rst_n)begin if(!rst_n)begin vld_out <= 1'b0; end else begin vld_out <= vld_in; end end always@(posedge clk or negedge rst_n)begin if(!rst_n)begin dout <= 0; end else begin dout <= a_ff0 * b_ff0 * c_ff0 * d_ff0; end end //always@(posedge clk or negedge rst_n)begin // if(!rst_n)begin // dout1 <= 0; // end // else begin // dout1 <= a_ff0 * b_ff0; // end //end // //always@(posedge clk or negedge rst_n)begin // if(!rst_n)begin // dout2 <= 0; // end // else begin // dout2 <= c_ff0 * d_ff0; // end //end // //always@(posedge clk or negedge rst_n)begin // if(!rst_n)begin // dout <= 0; // end // else begin // dout <= dout1 * dout2; // end //end endmodule |
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