【verilog_3】: 设计一个可以预置分频器，最大分频系数为 100000

设计一个可以预置分频器，最大分频系数为 100000

Design a preset frequency divider with a maximum frequency dividing coefficient of 100000.

author : Mr.Mao
e-mail : 2458682080@qq.com

module freq_div
#(
	parameter N = 17 
)
(			
	input clk,
	input reset_n,
	input [N-1:0] period_param,  //周期
	input [N-1:0] duty_param,   //占空比
	output reg div_out
);
	reg [N-1:0] cnt;
	
	always @(posedge clk or negedge reset_n)
		if(!reset_n)
			cnt <= 0;
		else if(cnt < period_param-1)
			cnt <= cnt + 1'b1;
		else
			cnt <= 0;
				
	always @(posedge clk or negedge reset_n)
		if(!reset_n)
			div_out <= 0;
		else if(cnt < duty_param-1)
			div_out <= 1'b1;
		else 
			div_out <= 0;

endmodule