verilog之分频大全

verilog各种分频大全——50占空比三分频

偶数分频

时序图

代码

module div_even (
    input clk,
    input rst_n,
    output clk_out      
);
parameter DIV_N = 4; //分频系数
reg [15:0] div_cnt;
reg clk_out_reg;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        div_cnt <= 0;
    end
    else begin
        if (div_cnt == (DIV_N-1)) begin
            div_cnt <= 0;
        end
        else begin
            div_cnt <=  div_cnt + 1;
        end
    end    
end
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        clk_out_reg <= 0;
    end
    else begin
        if (div_cnt == ((DIV_N / 2)-1)) begin
            clk_out_reg <= 1;
        end
        else if (div_cnt == (DIV_N-1)) begin
            clk_out_reg <= 0;
        end
        else begin
            clk_out_reg <= clk_out_reg;
        end
    end
end
assign clk_out = clk_out_reg;

endmodule

testbench及仿真图

module div_even_tb;

  // Parameters
 parameter DIV_N = 4;
  // Ports
  reg clk = 0;
  reg rst_n = 0;
  wire clk_out;

  div_even # (
      .DIV_N(DIV_N)
  )
  div_even_dut (
    .clk (clk ),
    .rst_n (rst_n ),
    .clk_out  ( clk_out)
  );

  initial begin
    begin
      #50 rst_n <= 1;
    end
  end

  always
    #5  clk = ! clk ;

endmodule

50％占空比的奇数分频

时序图

代码

//奇数分频，50％占空比
module div_odd (
    input clk,
    input rst_n,
    output clk_out  
);
parameter DIV_N = 3;
reg [15:0] div_cnt;
reg clk_1,clk_2;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        div_cnt <= 0;
    end
    else begin
        if (div_cnt == (DIV_N-1)) begin
            div_cnt <= 0;
        end
        else begin
            div_cnt <=  div_cnt + 1;
        end
    end    
end
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        clk_1 <= 0;
    end
    else begin
        if (div_cnt == (DIV_N-1)) begin
            clk_1 <= 0;
        end
        else if (div_cnt == ((DIV_N-1)/2)) begin
            clk_1 <= 1;
        end
        else begin
            clk_1 <= clk_1;
        end
    end
end
always @(negedge clk or negedge rst_n) begin
    if (!rst_n) begin
        clk_2 <= 0;
    end
    else begin
        if (div_cnt == (DIV_N-1)) begin
            clk_2 <= 0;
        end
        else if (div_cnt == ((DIV_N-1)/2)) begin
            clk_2 <= 1;
        end
        else begin
            clk_2 <= clk_2;
        end
    end
end

assign clk_out = clk_1 | clk_2;

endmodule //div_odd

testbench及仿真图

module div_odd_tb;

// Parameters
localparam  DIV_N = 5;

// Ports
reg clk = 0;
reg rst_n = 0;
wire clk_out;

div_odd 
#(
  .DIV_N (DIV_N )
)
div_odd_dut (
  .clk (clk ),
  .rst_n (rst_n ),
  .clk_out  ( clk_out)
);

initial begin
  begin
    #55 rst_n <= 1;
  end
end

always
  #5  clk = ! clk ;

endmodule

50％占空比的3分频

50％占空比的5分频

小数分频

代码

module div_decimals#(
    parameter C = 250,  //每C个clk_in时钟，
    parameter N = 3,    //输出N个clk_out时钟。
    parameter p = 83,   //C/N的商，
    parameter q = 1     //C/N的余数
)
(
    input clk_in,
    input rst_n,
    output clk_out 
    );
reg [15:0] mode_cnt;
reg mode;
reg [15:0] cnt;
reg clk_out_reg;

always @(posedge clk_in or negedge rst_n) begin
    if (!rst_n) begin
        cnt <= 0;
        clk_out_reg <= 0;
        mode_cnt <= 0;
        mode <= 0;
    end
    else begin
        case (mode)
            0:begin
                if (mode_cnt == q) begin
                    mode <= 1;
                    cnt <= cnt + 1;
                end
                else begin
                    if (cnt == (p+1-1)) begin
                        cnt <= 0;
                        clk_out_reg <= 0;
                        mode_cnt <= mode_cnt + 1;
                    end
                    else begin 
                        if (cnt == ((p+1-1)/2)) begin
                            clk_out_reg <= 1;
                            cnt <= cnt + 1;
                        end
                        else begin
                            cnt <= cnt + 1;
                        end
                    end
                end
            end
            1:begin
                if (mode_cnt == N) begin
                    mode <= 0;
                    mode_cnt <= 0;
                    cnt <= cnt + 1;
                end
                else begin
                    if (cnt == (p-1)) begin
                        cnt <= 0;
                        clk_out_reg <= 0;
                        mode_cnt <= mode_cnt + 1;
                    end
                    else begin
                        if (cnt == ((p-1)/2)) begin
                            clk_out_reg <= 1;
                            cnt <= cnt + 1;
                        end
                        else begin
                            cnt <= cnt + 1;
                        end
                    end
                end
            end
        endcase
    end
end

assign  clk_out = clk_out_reg;

reg [31:0] cnt_test;
always @(posedge clk_in or negedge rst_n) begin
    if (!rst_n) begin
        cnt_test <= 0;
    end
    else
        cnt_test <= cnt_test + 1;
end

endmodule

testbench及仿真图

module div_decimals_tb;

// Parameters
localparam  C = 250;
localparam  N = 3;
localparam  p = 83;
localparam  q = 1;

// Ports
reg clk_in = 0;
reg rst_n = 0;
wire clk_out;

div_decimals 
#(
  .C(C ),
  .N(N ),
  .p(p ),
  .q (
      q )
)
div_decimals_dut (
  .clk_in (clk_in ),
  .rst_n (rst_n ),
  .clk_out  ( clk_out)
);

initial begin
  begin
    #55 rst_n <= 1;
  end
end

always
  #5  clk_in = ! clk_in ;

endmodule

250/3分频

250/3分频，3个慢时钟对应250个快时钟

倍频

代码

testbench及仿真图