FPGA入门四简单状态机

状态机初步

verilong文件

module Hello(Clk,Rst_n,data,led);
 
  input Clk;
  input Rst_n;
  input [7:0]data;  //判断输入的字符字母ascall码 8位
  output reg led;
  
  
  //定义状态
  localparam 
    Scan_H =  5'b0_0001,
    Scan_e =  5'b0_0010,
    Scan_la = 5'b0_0100,
    Scan_lb = 5'b0_1000,
	 Scan_o =  5'b1_0000;
  
   reg [4:0]state;   //状态赋值寄存器

//一段式状态机  两段式状态机  三段式状态机
    always @(posedge Clk or negedge Rst_n)
	  if(!Rst_n) begin
	    state <= Scan_H;
		 led <= 1'b1;
		 end
		 else   begin
	            	 case(state)
		      Scan_H : if(data == "H")
				              state <= Scan_e;
								 else state <= Scan_H;
								 
				Scan_e : if(data == "e")
				            state <= Scan_la;
						     else state <= Scan_H;
							  	
				Scan_la : if(data == "l")
				            state <= Scan_lb;
							  else state <= Scan_H;
				
				Scan_lb : if(data == "l")
				            state <= Scan_o;
							else state <= Scan_H;
				
				Scan_o : begin	
			            state <= Scan_H;
				         if(data == "o")
				             led <= ~led;
								else led <= led;
			                                 end
		      default  state <= Scan_H;
		 endcase
  end

endmodule

仿真文件

`timescale 1ns/1ns
`define period_Clk 20

module Hello_tb;

  reg Clk;
  reg Rst_n;
  reg [7:0]ASCII;
  wire led;

Hello Hello0(
     .Clk(Clk),
	  .Rst_n(Rst_n),
	  .data(ASCII),
	  .led(led)
	  );
   
	
	initial  Clk = 1;
	always #(`period_Clk/2) Clk <= ~Clk;
   initial begin
	Rst_n=0;
	ASCII=0;
	#(`period_Clk*100);
	Rst_n = 1;
	#(`period_Clk*100);
	 forever  begin
	   ASCII = "r";
	  #(`period_Clk); 
	   ASCII = "g";
	   #(`period_Clk);
	   ASCII = "H";
	  #(`period_Clk); 
	   ASCII = "h";
		
		#(`period_Clk);
	   ASCII = "H";
	  #(`period_Clk); 
	   ASCII = "e";
	   #(`period_Clk);
	   ASCII = "L";
	  #(`period_Clk); 
	   ASCII = "H";
		
		#(`period_Clk);
	   ASCII = "e";
	  #(`period_Clk); 
	   ASCII = "l";
	   #(`period_Clk);
	   ASCII = "l";
	  #(`period_Clk); 
	   ASCII = "o";
      
      #(`period_Clk);
	   ASCII = "e";
	  #(`period_Clk); 
	   ASCII = "l";
	   #(`period_Clk);
	   ASCII = "l";
	  #(`period_Clk); 
	   ASCII = "o";

     #(`period_Clk);
	   ASCII = "e";
	  #(`period_Clk); 
	   ASCII = "j";
	   #(`period_Clk);
	   ASCII = "l";
	  #(`period_Clk); 
	   ASCII = "a";		
	 end
     
	end
	 

endmodule

仿真结果