8位计数器Timer--状态机VHDL

1. 设计要求
   

2. 提示分析状态表及流程图
   
   

3. 代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- **************************************
entity Timer is
port
(
	data_in :in std_logic_vector(7 downto 0);
	reset,clock,start:in std_logic;
	ring :out std_logic
);
end Timer;
-- **************************************
architecture behv of Timer is
type state is(st0,st1,st2,st3);
signal current_state,next_state:state;
signal counter :std_logic_vector(7 downto 0);
begin 

	COM1:process(clock,reset)
	begin 
		if reset='0' then current_state<=st0;		-- 时序
		elsif clock='1' and clock'event then 
			current_state<=next_state;
		end if;
	end process COM1;
-- **************************************	
	COM2:process(current_state,start,counter)   --状态切换
	begin 
		case current_state is
			when st0=> ring<='0';
				if start='1'then next_state<=st1;
				else next_state<=st0;
				end if;
			when st1=> 
				if start ='0' then next_state<=st2;
				else next_state<=st1;
				end if;
			when st2=>
				if counter=1 then next_state<=st3;
				else next_state<=st2;
				end if;
			when st3=> ring<='1';
				if counter /=1 then next_state<=st3;
				else next_state<=st0;
				end if;
			end case;
	end process COM2;
-- **************************************
	COM3:process(clock)								--计数
	begin 
		if clock='1' and clock'event then 
			case current_state is
				when st0=> counter<="00000000";
				when st1=> counter<=data_in;
				when st2=>
					if counter=1 then counter<="00001000";
					else
						counter<=counter-1;
					end if;
				when st3=> 
					if counter /=1 then
						counter<=counter-1;
					else counter<="00000000"; --改进
					end if;
				end case;
			end if;
	end process COM3;
end behv;
	

5. 设计波形
   
6. 问题分析
   问题波形
   

   原因：状态切换时没有进行清零
   改进：添加倒数第六行代码