verilog
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HDLBits 练习题(51-80)
51. Truth tables module top_module( input x3, input x2, input x1, // three inputs output f // one output ); assign f = (~x3 & x2) | ((x2 | x3) & x1); endmodule 52. Two-bit equality module top_module ( input [1:0]原创 2021-06-24 10:05:10 · 208 阅读 · 0 评论 -
HDLBits 练习题(29-50)
29. Always blocks (combination) // synthesis verilog_input_version verilog_2001 module top_module( input a, input b, output wire out_assign, output reg out_alwaysblock ); assign out_assign = a & b; always @(*) begin o原创 2021-06-24 10:04:08 · 130 阅读 · 0 评论 -
HDLBits 练习题(1-28)
题目地址:HDLBits 1. Getting Started module top_module( output one ); // Insert your code here assign one = 1'b1; endmodule 2. Output Zero module top_module( output zero );// Module body starts after semicolon assign zero = 1'b0;原创 2021-06-21 10:41:39 · 402 阅读 · 0 评论