转载自:https://www.cnblogs.com/ninghechuan/p/9828705.html
题目:多时钟域设计中,如何处理跨时钟域
- 单bit:两级触发器同步(适用于慢到快)
- 多bit:采用异步FIFO,异步双口RAM
- 加握手信号
- 格雷码转换
题目:编写Verilog代码描述跨时钟域信号传输,慢时钟域到快时钟域
reg [ 1: 0] signal_reg;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
signal_reg <= 2'b00;
else
signal_reg <= {signal_reg[0], signal_in};
end
assign signal_out = signal_reg[1];
题目:编写Verilog代码描述跨时钟域信号传输,快时钟域到慢时钟域
跨时钟域处理从快时钟域到慢时钟域,如果是下面第一个图,clkb则可以采样到signal_a_in,但是如果只有单脉冲,如第二个图,则不能确保采样到signal_a_in。这个时候用两级触发器同步是没有用的。
module Sync_Pulse(
input wire clka ,
input wire clkb ,
input wire rst_n .
input wire pluse_a ,
output wire pluse_b ,
output wire signal_outb
);
reg signal_a;
reg signal_b;
reg [ 1: 0] signal_b_reg;
reg [ 1: 0] signal_a_reg;
// 对signal_a进行展宽
always @(posedge clka or negedge rst_n) begin
if(!rst_n)
signal_a <= 1'b0;
else if(pluse_a)
signal_a <= 1'b1;
else if (signal_a_reg[1])
signal_a <= 1'b0;
else
signal_a <= signal_a;
end
always @(posedge clkb or negedge rst_n) begin
if(!rst_n)
signal_b <= 1'b0;
else
signal_b <= signal_a;
end
always @(posedge clkb or negedge rst_n) begin
if(!rst_n)
signal_b_reg <= 2'b00;
else
signal_b_reg <= {signal_b_reg[0], signal_b};
end
assign pluse_b = signal_b_reg[0] & ~signal_b_reg[1];
assign signal_outb = signal_b_reg[1];
always @(posedge clka or negedge rst_n) begin
if(!rst_n)
signal_a_reg <= 2'b00;
else
signal_a_reg <= {signal_a_reg[0], signal_b_reg[1]};
end
endmodule
题目:边沿检测
reg [ 1: 0] signal_reg;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
signal_reg <= 2'b00;
else
signal_reg <= {signal_reg[0], signal_in};
end
assign signal_posedge = signal_reg[0] & ~signal_reg[1];
assign signal_negedge = ~signal_reg[0] & signal_reg[1];