HDLBits 练习题(51-80)

51. Truth tables

module top_module( 
    input x3,
    input x2,
    input x1,  // three inputs
    output f   // one output
);
    
    assign f = (~x3 & x2) | ((x2 | x3) & x1);

endmodule

52. Two-bit equality

module top_module ( 
    input [1:0] A, 
    input [1:0] B, 
    output z 
); 
    
    assign z = (A == B)? 1'b1: 1'b0;

endmodule

53. Simple circuit A

module top_module (input x, input y, output z);
    
    assign z = (x ^ y) & x;

endmodule

54. Simple circuit B

module top_module ( 
    input x, 
    input y, 
    output z 
);
    
    assign z = ~(x ^ y);

endmodule

55. Combine circuits A and B

module top_module (input x, input y, output z);
    
    wire A1, B1, A2, B2;
    wire C1, C2;
    
    assign A1 = (x ^ y) & x;
    assign A2 = A1;
    assign B1 = ~(x ^ y);
    assign B2 = B1;
    
    assign C1 = A1 | B1;
    assign C2 = A2 & B2;
    
    assign z = C1 ^ C2;
    

endmodule

56. Ring or vibrate

module top_module (
    input ring,
    input vibrate_mode,
    output ringer,       // Make sound
    output motor         // Vibrate
);
    
    assign ringer = (ring & ~vibrate_mode) ? 1'b1: 1'b0;
    assign motor = (ring & vibrate_mode) ? 1'b1: 1'b0;

endmodule

57. Thermostat

module top_module (
    input too_cold,
    input too_hot,
    input mode,
    input fan_on,
    output heater,
    output aircon,
    output fan
); 
    
    assign heater = (mode & too_cold) ? 1'b1: 1'b0;
    assign aircon = (~mode & too_hot) ? 1'b1: 1'b0;
    assign fan = (heater | aircon | fan_on) ? 1'b1: 1'b0;
    

endmodule

58. 3-bit population count

module top_module( 
    input [2:0] in,
    output [1:0] out );
    
    assign out = in[0] + in[1] + in[2];
    
endmodule

59. Gates and vectors

module top_module( 
    input [3:0] in,
    output [2:0] out_both,
    output [3:1] out_any,
    output [3:0] out_different );
    
    assign out_both = {in[3] & in[2], in[2] & in[1], in[1] & in[0]};
    assign out_any = {in[3] | in[2], in[2] | in[1], in[1] | in[0]};
    assign out_different = {in[3] ^ in[0], in[2] ^ in[3], in[1] ^ in[2], in[0] ^ in[1]};

endmodule

60. Even longer vectors

module top_module( 
    input [99:0] in,
    output [98:0] out_both,
    output [99:1] out_any,
    output [99:0] out_different );
    
    wire 	[99: 0] both_reg = in >> 1;
    wire	[99: 0]	any_reg = in << 1;
    wire	[99: 0] diff_reg = {in[0], in[99:1]};
    
    wire [99: 0]	mid1 = both_reg & in;
    assign out_both = mid1[98: 0];
    
    wire [99: 0]	mid2 = in | any_reg;
    assign out_any = mid2[99:1];
    
    assign out_different = diff_reg ^ in;

endmodule

61. 2-to-1 multiplexer(选择器)

module top_module( 
    input a, b, sel,
    output out ); 
    
    assign out = sel?b: a;

endmodule

62. 2-to-1 bus multiplexer

module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out );
    
    assign out = sel ? b: a;

endmodule

63. 9-to-1 multiplexer

module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );
    
    always @(*) begin
        case(sel)
            4'd0:   out = a;
            4'd1:   out = b;
            4'd2:   out = c;
            4'd3:   out = d;
            4'd4:   out = e;
            4'd5:   out = f;
            4'd6:   out = g;
            4'd7:   out = h;
            4'd8:   out = i;
            default:out = 16'hffff;                
        endcase
    end

endmodule

64. 256-to-1 multiplexer

module top_module( 
    input [255:0] in,
    input [7:0] sel,
    output out );
    
    assign out = in[sel];

endmodule

65. 256-to-1 4-bit multiplexer

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
    
    assign out = in[sel*4+: 4];

endmodule

66. Half adder(半加器)

A half adder adds two bits (with no carry-in) and produces a sum and carry-out.

module top_module( 
    input a, b,
    output cout, sum );
    
    assign {cout, sum} = a + b;

endmodule

67. Full adder(全加器)

module top_module( 
    input a, b, cin,
    output cout, sum );
    
    assign {cout, sum} = a + b + cin;

endmodule

68. 3-bit binary adder

module top_module( 
    input [2:0] a, b,
    input cin,
    output [2:0] cout,
    output [2:0] sum );
    
    full_adder full_adder1( .a(a[0]), .b(b[0]), .cin(cin    ), .sum(sum[0]), .cout(cout[0]) );
    full_adder full_adder2( .a(a[1]), .b(b[1]), .cin(cout[0]), .sum(sum[1]), .cout(cout[1]) );
    full_adder full_adder3( .a(a[2]), .b(b[2]), .cin(cout[1]), .sum(sum[2]), .cout(cout[2]) );
   

endmodule

module full_adder( input 	a, input 	b,input 	cin, output 	sum, output 	cout );
    
    assign {cout, sum} = a + b + cin;
endmodule

69. Adder

module top_module (
    input [3:0] x,
    input [3:0] y, 
    output [4:0] sum);
    
    wire [3:0]	cout;
    wire [3:0]  sum_reg;
    
    genvar i;
    generate for(i=0; i<4; i=i+1) begin: genbit
        if(i==0)
            full_adder full_adder1( .a(x[0]), .b(y[0]), .cin(1'b0), .sum(sum_reg[0]), .cout(cout[0]) );
      	else
            full_adder full_adder2( .a(x[i]), .b(y[i]), .cin(cout[i-1]), .sum(sum_reg[i]), .cout(cout[i]) );                   
    end
    endgenerate
    
    assign sum = {cout[3], sum_reg};

endmodule

module full_adder( 
    input 	a, 
    input 	b,
    input 	cin, 
    output 	sum, 
    output 	cout );
    
    assign {cout, sum} = a + b + cin;
endmodule

70. Signed addition overflow

module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
); //
 
    assign s = a + b;
    assign overflow = (a[7] & b[7] & ~s[7]) | (~a[7] & ~b[7] & s[7]);

endmodule

71. 100-bit binary adder

module top_module( 
    input [99:0] a, b,
    input cin,
    output cout,
    output [99:0] sum );
    
    assign {cout, sum} = a + b + cin;

endmodule

72. 4-bit BCD adder

module top_module( 
    input [15:0] a, b,
    input cin,
    output cout,
    output [15:0] sum );
    
    wire [3: 0] cout_reg;
    genvar i;
    generate for(i=0; i<4; i=i+1) begin: gabit
        if(i==0)
            bcd_fadd bcd_fadd1 ( .a(a[3: 0]), .b(b[3: 0]), .cin(cin), .cout(cout_reg[3: 0]), .sum(sum[3: 0]) );
        else
            bcd_fadd bcd_fadd2 ( .a(a[i*4+: 4]), .b(b[i*4+: 4]), .cin(cout_reg[i-1]), .cout(cout_reg[i]), .sum(sum[i*4+: 4]) );
    end
    endgenerate
    
    assign cout = cout_reg[3];

endmodule

73. 3-variable

module top_module(
    input a,
    input b,
    input c,
    output out  ); 
    assign out = a | b | c;

endmodule

74. 4-variable

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  ); 
    
    assign out = (a & c & d) | (b & c &d) | (~b & ~c) | (~a &~d);

endmodule

75. 4-variable

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  );
    
    assign out = a | (~c & ~d & b) | (~a & ~b & c);

endmodule

76. 4-variable

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  ); 
    
    assign out = ((a ^ b) & ~c & ~d) | ((a^b)& c& d) | ((c^d) & a & b) | ((c^d) & ~a & ~b);

endmodule

77. Minimum SOP and POS

module top_module (
    input a,
    input b,
    input c,
    input d,
    output out_sop,
    output out_pos
); 
    
    assign out_sop = (c&d) | (~a&~b&c&~d);
    assign out_pos = (c&~b&~a) | (c&d&~a) | (c&d&b);

endmodule

78. Karnaugh map

module top_module (
    input [4:1] x, 
    output f );
    
    assign f = (~x[1] & x[3]) | (x[4] & x[2] & ~x[3]);

endmodule

79. Karnaugh map

module top_module (
    input [4:1] x,
    output f
); 
    
    assign f = (~x[3] & ~x[4] & ~x[2]) | ((~x[1] + x[2]) & x[3] & x[4]) | ((~x[1] + ~x[2]) & x[3] & ~x[4]) ;

endmodule

80. K-map implemented with a multiplexer

module top_module (
    input c,
    input d,
    output [3:0] mux_in
); 
    
    assign mux_in[0] = c | d;
    assign mux_in[1] = 0;
    assign mux_in[3] = c & d;
    assign mux_in[2] = ~d;

endmodule