博主也是初学verilog,若有错误,敬请指出!
1.双端口RAM
module ram2port #(parameter ADDR = 4, DEPTH = 2**ADDR, WIDTH = 8) (rst,in,out,write_clk,read_clk,write_en,read_en,read_addr,write_addr);
input [WIDTH - 1 : 0] in;
input write_clk;
input write_en;
input read_en;
input read_clk;
input rst;
input [ADDR - 1 : 0] read_addr;
input [ADDR - 1 : 0] write_addr;
output reg [WIDTH - 1 : 0] out;
reg [WIDTH - 1] mem [DEPTH - 1 : 0];
always@(posedge write_clk or negedge rst) begin
if(~rst) begin
for(integer i = 0 ; i < DEPTH ; i = i + 1) begin
mem[i] <= 0;
end
end
else if(write_en)
mem[write_addr] <= in;
end
always@(posedge read_clk) begin
if(read_en)
out <= mem[read_addr];
else
out <= 0;
end
endmodule
2.同步FIFO
module synfifo( clk, // syn clock
rst, //reset
write_en,
read_en,
out,
in,
empty,
full);
parameter WIDTH = 8;
parameter DEPTH = 16;
parameter ADDR = 4;
input clk;
input rst;
input write_en;
input read_en;
input[WIDTH:1] in;//