并行输入串行输出

你能给我个棒棒糖吗

已于 2022-03-06 21:42:31 修改

阅读量2.5k

点赞数

分类专栏： verilog 有限状态机文章标签：硬件工程

于 2022-03-06 21:41:01 首次发布

本文链接：https://blog.csdn.net/qq_44766436/article/details/123317834

版权

Verilog 有限状态机并行到串行转换数字逻辑硬件描述语言

关键词由CSDN通过智能技术生成

verilog 同时被 2 个专栏收录

6 篇文章 1 订阅

订阅专栏

有限状态机

2 篇文章 0 订阅

订阅专栏

利用有限状态机将并行输入的数据转换为串行输出，初学veirlog，如有错误，敬请指出。

1.RTL代码

module par2ser(in,
	       en,
	       clk,
	       rst,
	       ack,
       	   out,
       	   valid);

input in;
input clk;
input rst;
input en;
output out;
output valid;//when output signal is becoming valid, valid = 1
output ack;// ask for new info

wire[3:0] in;
reg out;
reg[3:0] curr_state;
reg[3:0] next_state;

parameter IDLE = 3'b000,
	  BIT1 = 3'b001,
	  BIT2 = 3'b011,
	  BIT3 = 3'b010,
	  BIT4 = 3'b110,
	  FINISH = 3'b111,//finish recieving info
	  READY = 3'b101;//ready for recieve info

always@(posedge clk or negedge rst) begin 

	if(~rst)
		curr_state <= IDLE;
	else
		curr_state <= next_state;

end

always@(*) begin

	case(curr_state)
	IDLE:begin
		if(en)
			next_state = READY;
		else
			next_state = IDLE;
	end
	READY:
		next_state = BIT1;
	BIT1:
		next_state = BIT2;
	BIT2:
		next_state = BIT3;
	BIT3:
		next_state = BIT4;
	BIT4:
		next_state = FINISH;
	FINISH:
		next_state = IDLE;

	default:next_state = IDLE;
	endcase
end

always@(posedge clk or negedge rst) begin

	if(~rst)
		out <= 0;
	else begin
		case(curr_state)
			BIT1:
				out <= in[0];
			BIT2:
				out <= in[1];
			BIT3:
				out <= in[2];
			BIT4:
				out <= in[3];
			default:out <= 0;
		endcase
	end
end

assign ack = (curr_state == FINISH);
assign valid = (curr_state == BIT1);

endmodule

2.testbench

module par2sertb;

reg clk;
reg rst;
reg en;
reg[3:0]in;
wire out;
wire ack;
wire valid;

initial begin
	
	`ifdef VCD 
		$vcdpluson;
	`endif
	rst = 0;
	en = 0;
	in = 0;
	#100 rst = 1;
	#100 en = 1;
	#10000 $finish;
end

initial begin
	
	clk = 0;
	forever #10 clk = ~clk;
end

always@(negedge ack) begin

	in = {$random} % 15;

end

par2ser u(.clk(clk),.rst(rst),.en(en),.out(out),.in(in),.ack(ack),.valid(valid));

endmodule