计数器verilog代码(quartus II)

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已于 2022-03-05 23:01:30 修改

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分类专栏： verilog 文章标签： fpga开发硬件工程

于 2022-03-04 22:55:56 首次发布

本文链接：https://blog.csdn.net/qq_44766436/article/details/123286223

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模十计数器

该计数器具有暂停和异步复位功能，初学verilog，如有错误，敬请指出！

1.verilog代码

module counter10(clk,rst,pause,out,counter);

input clk;
input rst;
input pause;
output out;
output counter;

reg[3:0] counter;

always@(posedge clk or negedge rst)begin

	if(~rst) 
			counter <= 4'b0000;
	else if(pause) 	
			counter <= counter;
	else if(counter == 4'b1001)	
			counter <= 4'b0000;
	else 
			counter <= counter + 1;
end

assign out = counter[3] & counter[0];

endmodule

2.testbench

`timescale 1ns/1ns
module counter10tb;

reg clk;
reg rst;
reg pause;
wire out;
wire[3:0] counter;
initial begin

	clk = 0;
	rst = 0;
	pause = 0;
	#22 rst = 1;
	#500 pause = 1;
	#100 pause = 0;
	#1000 $finish;

end

always #10 clk = ~clk;

counter10 u(.clk(clk),.rst(rst),.pause(pause),.out(out),.counter(counter));

endmodule