FPGA之乒乓操作

RTL代码

module fsm(
	input clk,
	input rst_n,
	input [7:0]data_in,
	output reg[7:0]data_out
);

	reg [7:0]data_buffer1;
	reg [7:0]data_buffer2;
	reg wr_buf1;
	reg wr_buf2;
	
	reg [1:0]c_state;
	reg [1:0]n_state;
	parameter s0 = 2'b01;
	parameter s1 = 2'b10;
	
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			c_state <= s0;
		else
			c_state <= n_state;
	end
	
	always@(*)begin
		case(c_state)
			s0:begin
				n_state <= s1;
			end
			s1:begin
				n_state <= s0;
			end
			default:n_state <= s0;
		endcase
	end
	
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			wr_buf1 <= 1'b0;
			wr_buf2 <= 1'b0;
		end
		else if(n_state <= s0)begin
			wr_buf1 <= 1'b1;
			wr_buf2 <= 1'b0;
		end
		else if(n_state <= s1)begin
			wr_buf1 <= 1'b0;
			wr_buf2 <= 1'b1;
		end
		else begin
			wr_buf1 <= 1'b0;
			wr_buf2 <= 1'b0;
		end
	end
	
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			data_buffer1 <= 'd0;
			data_buffer2 <= 'd0;
		end
		else if(wr_buf1)begin
			data_buffer1 <= data_in;
			data_buffer2 <= data_buffer2;
		end
		else if(wr_buf2)begin
			data_buffer2 <= data_in;
			data_buffer1 <= data_buffer1;
		end
	end
	
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			data_out <= 'd0;
		end
		else if(wr_buf1)begin
			data_out <= data_buffer2;
		end
		else if(wr_buf2)begin
			data_out <= data_buffer1;
		end
	end


endmodule