VHDL 交通灯

Entity traffic is
Port(clk,rst:in std_logic;
         led:out std_logic_vector(5 downto 0));
end traffic;
Architecture behavior of traffic is
signal cnt:std_logic_vector(5 downto 0);
type traffic_st is(westg,westy,northg,northy);
signal st_traffic:traffic_st;
begin
process(clk,rst)
begin
if rst='0' then
    cnt<="000000"
    led<="000000";
    st_traffic<=westg;
elsif rising_edge(clk) then
    case st_traffic is
    when westg=>
    led<="001100";
    if cnt=29 then
        cnt<="000000";
        st_traffic<=westy;
    else
        cnt<=cnt+1;
    end if;
    when westy=>
    led<="010100";
    if cnt=5 then
        cnt<="000000";
        st_traffic<=northg;
    else
        cnt<=cnt+1;
    end if;
    when northg=>
    led<="100001";
    if cnt=29 then    
        cnt<="000000";        
        st_traffic<=northy;    
    else
        cnt<=cnt+1;    
    end if;
    when northy=>
    led<="100010";    
    if cnt=5 then  
        cnt<="000000";        
        st_traffic<=westg; 
    else        
        cnt<=cnt+1;   
    end if;
    when others=>
    end case;
end if;
end process;