verilog 相邻点累加。

`timescale 1ns/10ps
module sigma_16p(
				clk,
				res,
				data_in,
				syn_in,	
				data_out,
				syn_out
);
input clk,res, syn_in;//sys采样时钟
input[7:0] data_in;//采样信号
output	syn_out;//累加结果同步脉冲
output[11:0] data_out;//累加结果

reg sys_in_n1;//采样时钟的反向延时
reg[3:0] con_sys;
reg[11:0] sigma;
reg[11:0] data_out;
reg syn_out;

wire sys_pulse;//识别采样时钟上升沿
wire[7:0] comp_8; //补码
wire[11:0] d_12; //升位结果


//assign sys_in_n1=~syn_in;
assign sys_pulse=sys_in_n1&syn_in;
assign comp_8=data_in[7]?{data_in[7],~data_in[6:0]+1}:data_in;
assign d_12={comp_8[7],comp_8[7],comp_8[7],comp_8[7],comp_8};

always@(posedge clk or negedge res)
if(~res) begin
   sys_in_n1<=0;
   con_sys<=0;
   sigma<=0;
   data_out<=0;
   syn_out<=0;
end
else begin
   sys_in_n1<=~syn_in;
   if(sys_pulse==1)begin
      con_sys<=con_sys+1;
     if(con_sys==15)begin
     		 sigma<=d_12;
     		 data_out<=sigma;
     		 syn_out<=1;
     end
       else begin
        sigma<=sigma+d_12;
         syn_out<=0; 
         end
         end
end
endmodule

module sigma_16p_tb;
reg clk,res,syn_in;
reg[7:0] data_in;
wire[11:0] data_out;
wire syn_out;
sigma_16p sigma_16p(
				.clk(clk),
				.res(res),
				.data_in(data_in),
				.syn_in(syn_in),	
				.data_out(data_out),
				.syn_out(syn_out)
);
initial	begin
			 				clk<=0;res<=0;data_in<=1;syn_in<=0;		
				#10			res<=1;
				#25000					$stop;
end

always #5 clk=~clk;
always #100 syn_in=~syn_in;
endmodule