Verilog-A 实现开关电流源

Verilog-A 实现开关电流源

行为模型的代码如下，实现的功能为当TX为高电平时，电流源导通为输出端的电容放电，否则保持关断

// VerilogA for test, pd_and_tx, veriloga

`include "constants.vams"
`include "disciplines.vams"

module pd_and_tx(iphoto_tx, TG);

input  TG       ;
output iphoto_tx;

ground gnd;

parameter real tx_vth = 1.7 ;
parameter real iphoto = 200p;

electrical TG       ;
electrical iphoto_tx;

real mid_iphoto_tx  ;

analog begin
    @(initial_step) begin
        mid_iphoto_tx = 0.0              ;
    end
    //if TG passes through vth from bottom to top
    @(cross(V(TG) - tx_vth,  1)) begin
        mid_iphoto_tx = iphoto;
    end
    //if TG passes through vth from bottom to top
    @(cross(V(TG) - tx_vth, -1)) begin
        mid_iphoto_tx = 0.0;
    end
    I(iphoto_tx, gnd) <+ mid_iphoto_tx;
end