Alwaysblock1

Alwaysblock1

关于 wire vs. reg 的说明：assign 语句的左侧必须是网络类型（例如，连线），而过程赋值的左侧（在 always 块中）必须是变量类型（例如，reg）。这些类型（wire vs. reg）与合成的硬件无关，只是Verilog用作硬件模拟语言时遗留下来的语法。

A note on wire vs. reg: The left-hand-side of an assign statement must be a net type (e.g., wire), while the left-hand-side of a procedural assignment (in an always block) must be a variable type (e.g., reg). These types (wire vs. reg) have nothing to do with what hardware is synthesized, and is just syntax left over from Verilog’s use as a hardware simulation language.