IA （Instrumentation Amplifier）

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Topologies

Three-Opamp Topology

Switched-Capacitor Topology

Capacitively-Coupled Topology

Current-Mode Topology

Current-Feedback Topology

Dynamic Offset Cancellation Techniques

Trimming

Auto-Zeroing

output offset storage

Input Offset Storage

Closed-Loop Offset Cancellation with Auxiliary Amplifier

Conclusion of Auto-Zeroing

Chopping

Charge injection and clock feed-through

Compensation techniques for charge injection

Chopper amplifier's residual offset

内容来源：Precision instrumentation amplifiers and read-out integrated circuits

Topologies

The commonly used topologies are the classic three-opamp, switched-capacitor, capacitively-coupled, current-mode and current-feedback instrumentation amplifiers (IAs).

Three-Opamp Topology

a fully-differential three-opamp IA — A fully-differential three-opamp IA

uses voltage feedback to obtain a gain determined by resistors; the first stage
is a fully-differential amplifier with a gain of $\frac{R_{21}+R_{1}+R_{22}}{R_{1}}$ and the second
stage is a differential amplifier
CMRR: determined by the product of the finite gain of its first stage, and the finite CMRR of its second stage; The latter is determined by the matching of the feedback resistors R3-R6, which usually leads to a CMRR of about 80 dB
If a differential output is required, the first stage can be used alone, which is known as the two-opamp topology.
high input impedance
good linearity over a wide input and output range
can not sense the supply rails
not very power-efficien

Switched-Capacitor Topology

When clock $\phi_{1}$ is high, the input signal is sampled on capacitor C1, while the integration capacitor C2 is reset; When clock $\phi_{2}$ is high, the charge stored on C1 is transferred to C2
closed-loop gain of the IA is determined by C1/C2; this gain can achieve 0.1 % gain error and low drift over temperature
accommodates a large CM input range
can not provide a continuous signal
increases noise level due to noise folding, kT/C noise
To reduce noise, input capacitor C1 needs to be increased. but results in a decrease in the input impedance.

Capacitively-Coupled Topology

A Capacitivelycoupled instrumentation amplifier

employs an input chopper to convert the input DC signal into an AC signal, an output chopper then converts the amplified AC signal back to DC
its input impedance is typically in the order of several MΩ, and can be increased to a few tens of MΩ by using an impedance boosting technique
exhibits a rail-to-rail input CM range
very power-efficien, its power consumption is mainly dominated by Gm1
switched-chopper capacitor causes spikes (or glitches) and more noise at the amplifier output
capacitively-coupled IAs is more compatible with a SC sampled ADC; with proper timing, sampling of the spikes at the IA output can be avoided and the non-continuous signal path is not an issue for a SC sampled ADC.

Current-Mode Topology

A current-mode instrumentation amplifier

The feedback around the input amplifiers A1 and A2 forces the input voltage across the resistor R1. The current through this resistor is mirrored by precision current mirrors and converted into a voltage by R2, and then buffered by the output opamp A3
the DC precision of the current mirrors is essential for the overall offset, gain accuracy, drift and linearity
CMRR: depends on the matching of the current-mirrors

Current-Feedback Topology

A current-feedback instrumentation amplifier

The overall feedback ensures that the output currents of Gm2 and Gm3 cancel and thus the amplifier’s gain is given by $Gain = \frac{G_{m2}}{G_{m3}}\frac{R_{1}+R_{21}+R{22}}{R1}$
CMRR: higher than the three-opamp topology, its CMRR is mainly determined by the CMRR of Gm2 and can be made greater than 120 dB
capable of handling input CM voltages include either of the supply rails
more power efficien
avoids noise folding
higher input impedance than the capacitively-coupled topology, and it does not produce output glitches
more suitable for use as a stand-alone IA
disadvantage: limited gain accuracy
the linear range of a CFIA is often limited by the input and feedback transconductors to several tens of mV

Error sources

At low frequencies, offset, 1/f noise and drift are the dominant error sources of operational amplifiers.

Offset--失调

In CMOS technology, the worst-case offset of a differential input pair can be as large as 10 mV
caused by manufacturing variation or uncertainty, such as threshold voltage mismatch and mismatch between the equivalent lengths and widths of nominally identical transistors
size mismatch can be reduced by using large devices. However, this increases chip area and therefore production cost.

1/f noise

mainly caused by the defects in the interface between the gate oxide and the silicon substrate, so it depends on the ‘‘cleanness’’ of the oxide-silicon interface and may be considerably different from one CMOS technology to another
The typical 1/f noise corner frequency of CMOS technology is in the order of
several kHz to tens of kHz, making the 1/f noise a dominant error source at low
frequencies
the 1/f noise can be modeled as a function of frequency:

$V_n^2=\frac{K}{WLC_{ox}f}$

Generally, 1/f noise in PMOS is much lower than NMOS in most technologies
to decrease 1/f noise, the device area must be increased. However, this again increases chip area.

Drift--偏移

caused by the cross-sensitivity of some error sources to temperature or time
Drift mainly manifests itself as offset drift and gain drift
it can be reduced by suppressing the offset and gain error to a low enough level, and furthermore by dynamically compensating for their temperature drift
Low drift is a critical requirement for precision temperature measurement, since the drift of the interface electronics can then not be distinguished from the sensor signal itself.

Dynamic Offset Cancellation Techniques

To reduce offset, three types of offset cancellation techniques can be applied: trimming, auto-zeroing, and chopping. The latter two are dynamic offset cancellation techniques.

Trimming

involves measuring and then reducing the offset during production
can be used to obtain an order-of-magnitude reduction of the offset
unable to reduce the initial mV-level offset below a few tens of μV
does not eliminate low-frequency noise, such as 1/f noise

Auto-Zeroing

dynamic offset cancellation technique; discrete-time sampling technique
three basic topologies for auto-zeroing: output offset storage (also called open-loop offset cancellation), input offset storage (also called closed-loop offset cancellation) and closed-loop offset cancellation using an auxiliary amplifier

output offset storage

auto-zeroing phase: CK is high; its inputs are shorte together; nodes X and Y are shorted together; When all the node voltages are settled, A * Vos is stored across C1 and C2
amplification phase: CK turns low, the differential input voltage together with Vos is amplified, and stored on C1 and C2. Since Vos is already stored on C1 and C2, VX and VY does not see Vos, which is fully cancelled
clock feed-through: When a switch opens, it injects some charge into the surrounding circuitry. This charge consists of gate-source/drain channel charge and charge injected through the overlap capacitances. The mismatch charge injection of S3 and S4 results in a residual offset, given by:

$V_{OS,res}=\frac{\frac{q_{inj3}}{C_{1}}-\frac{q_{inj4}}{C_2}}{A}$

A is typically chosen to be between 10 and 100
limits the maximum gain of the amplifie
introduce capacitors in the signal path. The bottom-plate parasitic of the capacitors
decreases the amplifier bandwidth, thus degrading its phase margin and stability.

Input Offset Storage

auto-zeroing phase: CK is high, the output and input of the amplifier are shorted together, placing the amplifier in a unity-gain configuration. When the node voltages are settled, the output voltage Vout is given by:

$V_{out}=\frac{A}{1+A}\cdot V_{os}$

The circuit reproduces the amplifier’s offset at nodes X and Y, storing the resulton C1 and C2. the input-referred offset voltage of the overall circuit equals VOS/A if S3 and S4 match perfectly

residual offset: If S3 and S4 have any mismatch, this will cause mismatch charge injection and, in turn, lead to a residual offset, which is given by:

$V_{res}\approx\frac{V_{OS}}{A+1}+(\frac{q_{inj3}}{C_1}-\frac{q_{inj4}}{C_2})$

the offset Vos is suppressed by the gain of the amplifier
The charge injection and the leakage of the capacitors can be reduced by increasing the size of the capacitors, but cannot be suppressed by the gain because the capacitors are directly at the amplifier input
introduce capacitors in the signal path. The bottom-plate parasitic of the capacitors decreases the amplifier bandwidth, thus degrading its phase margin and stability.

Closed-Loop Offset Cancellation with Auxiliary Amplifier

Auxiliary amplifier placed in a feedback loop during offset cancellation

mitigate the stability issue: closed-loop offset cancellation with an auxiliary amplifier can be used to isolate the offset storage capacitors from the signal path
auto-zeroing phase: the inputs of Gm1 are shorted, Vout can be calculated as:

$[G_{m1}V_{os1}-G_{m2}(V_{out}-V_{OS2})]R=V_{out,AZ}$

$V_{out,AZ}=\frac{G_{m1}RV_{OS1}+G_{m2}RV_{OS2}}{1+G_{m2}R}$

amplification phase: S3 and S4 turn off, voltage $V_{out,AZ}$ is stored on C1 and C2, the offset voltage referred to the main input is given by:

$V_{OS,res}=\frac{V_{out,AZ}}{G_{m1}R}\approx\frac{V_{OS1}}{G_{m2}R}+\frac{V_{OS2}}{G_{m1}R}$

The charge injection due to the mismatch of S3 and S4 contributes to the offset of Gm2. In order to attenuate this charge injection, Gm2 is usually chosen to be at least 50 times smaller than Gm1

Conclusion of Auto-Zeroing

Such amplifiers cannot provide a continuous-time output, unless a ping-pong topology is employed. These three offset cancellation techniques cancel offset by periodically subtracting the offset obtained during the previous sampling moment. This assumes that the offset does not change too much during the amplification time. These techniques also eliminate 1/f noise and drift. However, the sampling action of the auto-zeroing techniques affects the amplifier’s noise performance at frequencies below the sampling frequency.
Noise: auto-zeroing is a sampling technique. Noise bandwidth $f_{n,BW}$ (determined by the time constant of the system) is usually chosen to be larger than the auto-zeroing frequency $f_{AZ}$ , so that the under-sampled noise folds back to DC, increasing the noise PSD at the baseband.
The noise folding factor n is defined as:

$n=\frac{2f_{n,BW}}{f_{AZ}}$

Due to under-sampling, the noise power after sampling increases by this factor as compared to that before sampling. By choosing a small $f_{n,BW}$ , the folded noise can be restricted.

Chopping

continuous-time modulation technique, does not cause noise folding
Low-frequency errors, such as 1/f noise and drift will be modulated and filtered
out along with offset
ripple amplitude must be suppressed

time domain: The input voltage Vin first passes through a chopper driven by a clock at frequency fch, thus it is converted to a square wave voltage at fch. Next, the modulated signal is amplified together with its own input offset. The second chopper then demodulates the amplified input signal back to DC, and at the same time modulates the offset to the odd harmonics of fch, where they are filtered out by a low-pass filter (LPF). This results in an amplified input signal without offset.
frequency domain: At the beginning, the signal is modulated, and the noise and offset are superposed onto this modulated signal. After amplification and the second chopper, the modulated signal is demodulated back to DC, while the low-frequency noise and offset are modulated to the harmonics of the chopper frequency, appearing as a chopper ripple at the
amplifier output . A LPF is then used to remove the modulated offset and 1/f noise, resulting in a clean low-frequency signal without offset or 1/f noise.

the offset is amplified by the DC gain of A1, the signal is amplified by the effective gain of A1 at the chopping frequency fch. To maximize the effective gain of the stage consisting of A1 and two choppers, the optimum chopping frequency should be around 3 dB bandwidth of A1.

Simplified block diagram of a chopper amplifier

he peak-to-peak amplitude of the ripple can then be approximated as:

$V_{out,ripple}=\frac{Vos\cdot G_{m2}}{2C_{M1}\cdot f_{ch}}$

ripple amplitude can be reduced by reducing input-stage offset Vos with careful layout, by increasing the chopping frequency fch1 or by increasing the size of the Miller compensation capacitor.

Charge injection and clock feed-through

Compensation techniques for charge injection

1. Dummy switches

Charge injection can be partially compensated for by adding dummy switches that are driven by a complementary clock signal and that inject an amount of charge which compensates for the charge injected by the main switch.

The effectiveness of the compensation depends on the matching of the injected charges.
A clock signal with a high slew rate can be used to obtain an equal distribution of the channel charge in the main switch’s drain and source terminals
A half-size dummy switch can then be used for compensation
the assumption of equal splitting of the charge between the source and drain is generally
invalid, making this approach less attractive.

2. Complementary Switches

use both PMOS and NMOS devices such that the opposite charge packets injected by the two cancel each other
this cancellation is only effective for a limited range of the input signal around half of the supply voltage

3.Fully Differential Circuit

best way
If the charge injection in the two half circuits matches, the charge injection only results in a change in the common-mode voltage
A differential voltage change only results from charge-injection mismatch.

Chopper amplifier's residual offset

Charge injection model in a chopper amplifier

For chopper amplifiers, residual offset is mainly caused by three issues:

1. Non-idealities in clock timing

such as clock skew, non-overlap and overlap in chopper clocks introduce residual offset.

2. Demodulated clock feed-through current spikes

due to clock feed-through, the imbalance of parasitic capacitors in the choppers also causes a residual offset.

3.Impedance mismatch between two input nodesImpedance mismatch between two input nodes

Thirdly, the source impedance mismatch (DR = R1-R2) causes another residual offset.

These three errors can be minimized by:

1. Decreasing the chopping frequency

2. Decreasing the chopper clock amplitude

3. Balancing or minimizing the overlap capacitors between the clock lines to the input and output terminals of G1

4. Ensuring matched and balanced input impedance for differential paths reduces residual offset caused by the input bias current

Suppression Techniques

1. Nested-Chopper Technique

The nested chopper technique uses an extra pair of choppers that run at a much lower frequency.

The residual offset of the amplifier chopped by a high frequency chopper clock $\phi_{H}$ is chopped out by a low-frequency chopper clock $\phi_{L}$ . The overall residual offset is only limited by the charge injection in the lowfrequency chopper, and therefore it is reduced by a factor $\frac{f_{H}}{f_L}$ .

The useable signal bandwidth is reduced, since it is limited by $f_L$ rather than $f_H$ .

2. Filtering of Spike Harmonics

Chopper amplifier with an LP or BP
amplifier to remove clock feed-through spikes

Most of the energy of the chopper ripple is located at the first harmonics. Therefore, a low-pass (LP) or band-pass (BP) filter can be incorporated between the chopper switches to filter out the chopper harmonics at the high frequencies, at the cost of a small reduction in the signal bandwidth.

A disadvantage of this technique is the significant amount of extra circuitry required.

(处理的是chopper转换器件产生的高频毛刺，而不是有用的输入信号产生的偏移，所以在两级放大器之间加入filter滤掉一些毛刺产生的高频处的谐波)

3. Chopper with Guard Band

Introduce a small guard time in the output chopper switch that prevents the spikes caused by the input chopper from being demodulated

the residual offset with the guard band technique is limited by the matching between the shape of the spike and the guard time delay
the output signal is no longer continuous-time due to the gap in the guard time, incurring a slight loss of gain and noise aliasing.