matlab与FPGA的交互程序

1.比如现在我要在matlab上产生一个信号用于FPGA的仿真输入，所以需要将这个信号写到txt文本中去。代码如下

clc
clear all
f1=1*10^6;
fs=50*10^6;

L=2000;
t=0:L-1;
t=t/fs;
da=sin(2*pi*f1*t);
da=floor(da*127);  //量化8bit
N=8;
fid=fopen('d:\data.txt','w');

for i=1:length(da)
    da1=dec2bin(da(i)+(da(i)<0)*2^N,N)
    for j=1:N
     if da1(j)=='1';
        tb=1;
     else
        tb=0;
     end
       fprintf(fid,'%d',tb);
    end
    fprintf(fid,'\r\n');
end
fprintf(fid,':');
fclose(fid);

1.1还有一个在设计滤波器时滤波器系数可以通过Matlab写成coe文件导入到滤波器中

fs=8*10^6;
f1=2*10^6;
ps=1*10^6;
N=1000;
t=0:N-1;
t=t/fs;
s1=cos(2*pi*f1*t);

s=randn(1,N)>0;
for i=1:N
    if s(i)==0
        d(i)=0;
    else
        d(i)=1;
    end
    
end
da=rectpulse(d,fs/ps);
mt=da(1:N);    %基带信号

fn=0:N-1;
fn=fn/N*fs;

y1=s1.*mt;    %ask信号
figure(1)
subplot(411)
plot(t,mt); title('基带数据');
subplot(412)
plot(fn,abs(fft(mt)));title('基带数据的频谱');
subplot(413)
plot(t,y1);title('2ASK调制信号波形');
subplot(414)
plot(fn,abs(fft(y1)));title('2ASK调制信号频谱');


fc=1*10^6;
L=32;
% w=blackman(L)';
yb=abs(y1);
wn1=fc*2/fs;

b1=fir1(L,wn1);
y3=filter(b1,1,yb);
figure(2)
subplot(211)
plot(t,yb);title('经过整流后的2ASK波形');
subplot(212)
plot(fn,abs(fft(yb)));title('经过整流后的2ASK波形的频谱');
figure(3)
subplot(211)
plot(t,y3); title('低通滤波后的基带数据');
subplot(212)
plot(fn,abs(fft(y3)));title('低通滤波后的基带数据的频谱');


B=8;
da=b1/max(abs(b1));
da1=da*(2^(B-1)-1);
da8=round(da1);

fid=fopen('d:\data.coe','w');
fprintf(fid,'RADIX=10;\r\n');
fprintf(fid,'coefdata=\r\n');

for i=1:length(da8)
    if(i<length(da8))
fprintf(fid,'%d,\r\n',da8(i));
    else
 fprintf(fid,'%d;\r\n',da8(i)); 
    end
end
fclose(fid); 




sum=0;
for k=1:N
  sum=sum+y3(k)  

end

nu=sum/1000;


for j=1:N
        if y3(j)>(nu)
        d1(j)=1;
    else
        d1(j)=0;
    end
    end


figure(4)
plot(t,d1);title('门限判决后的基带数据');

2.那么在fpga程序怎么将这个TXT文本调用出来呢？

`timescale 1ns / 1ps


// Company: 
// Engineer:
//
// Create Date:   15:48:20 05/05/2021
// Design Name:   iir_top
// Module Name:   F:/iirz/tst.v
// Project Name:  iirz
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: iir_top
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 


module tst;

	// Inputs
	reg clk;
	reg rst;
	reg [11:0] din;

	// Outputs
	wire [11:0] dout;

	// Instantiate the Unit Under Test (UUT)
	iir_top uut (
		.clk(clk), 
		.rst(rst),
		.din(din), 
		.dout(dout)
	);

	
	  
	  parameter clk_period=626;
	  parameter clk_half_period=clk_period/2;
	  parameter data_num=2000;
	  parameter time_sim=data_num*clk_period/2;
	initial begin
		// Initialize Inputs
		clk = 0;
		rst =1;
		

		// Wait 100 ns for global reset to finish
		#10000;
      rst=0; 
		// Add stimulus here
     #time_sim $finish;
	  din=12'd10;
	end
	 integer pa=0;
	 reg [11:0] s1[1:data_num];
	 initial
	 begin
	   $readmemb("data.txt",s1);
		pa=0;
		repeat(data_num)
		  begin
		  pa=pa+1;
		  din=s1[pa];
		  #clk_period;
	end
	end 
always #clk_half_period clk<=!clk; 
	
      
endmodule

matlab读取txt文件并画图

%从文本中读取数据
%din为读取文件获得的数据，n为数据长度
fid=fopen('d:dout.txt','r');
[dout,n]=fscanf(fid,'%lg',inf);
fclose(fid);

fs=50*10^6;
N=length(dout);
t=0:N-1;
t=t/fs;

subplot(311)
plot(t,dout);

fid=fopen('d:din.txt','r');
[din,n]=fscanf(fid,'%lg',inf);
fclose(fid);

fs=50*10^6;
N1=length(din);
t1=0:N1-1;
t1=t1/fs;
N1=length(din)
subplot(312)
plot(t1,din);

fid=fopen('d:sine.txt','r');
[sine,n]=fscanf(fid,'%lg',inf);
fclose(fid);

fs=50*10^6;
N2=length(sine);
t2=0:N2-1;
t2=t2/fs;
subplot(313)
plot(t2,sine);