clc
clear all
f1=1*10^6;
fs=50*10^6;
L=2000;
t=0:L-1;
t=t/fs;
da=sin(2*pi*f1*t);
da=floor(da*127);
N=8;
fid=fopen('d:\m\data.txt','w');
fid1=fopen('d:\m\data1.txt','w');
fid2=fopen('d:\m\data2.txt','w');
fid3=fopen('d:\m\data3.txt','w');
for i=1:4:length(da)
da1=dec2bin(da(i)+(da(i)<0)*2^N,N)
for j=1:N
if da1(j)=='1';
tb=1;
else
tb=0;
end
fprintf(fid,'%d',tb);
end
fprintf(fid,'\r\n');
end
fprintf(fid,':');
fclose(fid);
for i=2:4:length(da)
da1=dec2bin(da(i)+(da(i)<0)*2^N,N)
for j=1:N
if da1(j)=='1';
tb=1;
else
tb=0;
end
fprintf(fid1,'%d',tb);
end
fprintf(fid1,'\r\n');
end
fprintf(fid1,':');
fclose(fid1);
for i=3:4:length(da)
da1=dec2bin(da(i)+(da(i)<0)*2^N,N)
for j=1:N
if da1(j)=='1';
tb=1;
else
tb=0;
end
fprintf(fid2,'%d',tb);
end
fprintf(fid2,'\r\n');
end
fprintf(fid2,':');
fclose(fid2);
for i=4:4:length(da)
da1=dec2bin(da(i)+(da(i)<0)*2^N,N)
for j=1:N
if da1(j)=='1';
tb=1;
else
tb=0;
end
fprintf(fid3,'%d',tb);
end
fprintf(fid3,'\r\n');
end
fprintf(fid3,':');
fclose(fid3);
sdfasfsaf
module tst;
// Inputs
reg clk;
reg [7:0] din;
// Outputs
wire [15:0] dout;
wire [7:0] sine;
// Instantiate the Unit Under Test (UUT)
df uut (
.clk(clk),
.din(din),
.sine(sine),
.dout(dout)
);
parameter data_num=1880;
parameter time_sim=data_num*20;
reg rst=1;
initial begin
// Initialize Inputs
rst=1;
clk = 1;
din = 8'd0;
// Wait 100 ns for global reset to finish
#100;rst=0;
// Add stimulus here
#time_sim $finish;
end
//从外部txt文件读取数据作为测试激励
always #10 clk<=!clk;
integer pattern=0;
reg [7:0] stimulus[1:data_num];
always@(posedge clk)
begin
$readmemb("data.txt",stimulus);
pattern=pattern+1;
din=stimulus[pattern];
end
//将仿真数据dout写入外部txt文件中
integer file_out;
integer file_out1;
integer file_out2;
initial
begin
file_out=$fopen("dout.txt"); //将文件放置在工程路径下
if(!file_out)
begin
$display("could not open file!");
$finish;
end
begin
file_out1=$fopen("din.txt");
end
begin
file_out2=$fopen("sine.txt");
end
end
//将输出数据写入指定文本文件中
wire rst_write;
//将dout转换成有符号数据
wire signed [15:0] dout_s;
assign dout_s=dout;
//产生写入时钟信号,复位状态时不写入数据
assign rst_write=clk&(!rst);
always@(posedge rst_write)
$fdisplay(file_out,"%d",dout_s);
//将dout转换成有符号数据
wire signed [7:0] din_s;
assign din_s=din;
//产生写入时钟信号,复位状态时不写入数据
always@(posedge rst_write)
$fdisplay(file_out1,"%d",din_s);
//将dout转换成有符号数据
wire signed [7:0] sine_s;
assign sine_s=sine;
//产生写入时钟信号,复位状态时不写入数据
always@(posedge rst_write)
$fdisplay(file_out2,"%d",sine_s);
endmodule