Schematic export failed or was cancelled. Please consult the transcript in the source windo

在版图画完进行LVS的时候弹出, Schematic export failed or was cancelled. Please consult the transcript in the source window

找到的解决方法

1.删除原理图文件夹下面你的.cdslck文件
2.通过ctrl+H 打开.bashrc文件,然后在最后一行输入
export CDS_Netlisting_Mode=Analog
查看环境变量是否导入成功:echo $CDS_Netlisting_Mode
在这里插入图片描述
也可以首先打开终端输入export CDS_Netlisting_Mode=Analog 做临时的环境变量,然后同一终端下运行vituoso跑lvs进行测试,测试成功再将环境变量写入.bashrc文件中,做成永久的环境变量。

环境变量的一篇参考文章:临时永久环境变量介绍
查找到的LVS出现该问题的帖子:解决办法讨论

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Sure, I can help you with that. Here is a labelled schematic diagram of an SR latch built using two NAND gates: ``` +-----+ +-----+ ----|NAND1|---------------| | +--+--+ | | |SR|---------------|NAND2| +--+--+ | | ----|NAND3|---------------| | +-----+ +-----+ ``` In this diagram, the inputs S (set) and R (reset) are connected to the two NAND gates. The output of NAND1 is connected to the input of NAND2, and the output of NAND2 is connected to the input of NAND3. The outputs of NAND1 and NAND3 are the complementary outputs Q and Q̅, respectively. To understand how an SR latch works, let's consider the following scenarios: 1. When S=0 and R=0: Both inputs of NAND1 and NAND3 are high, which means their outputs are low. This makes the input of NAND2 high, which in turn makes its output low. This maintains the previous state of the latch, and both Q and Q̅ remain unchanged. 2. When S=1 and R=0: The high input of NAND1 makes its output low, which sets the input of NAND2 to low. The low input of NAND3 makes its output high, which in turn makes the input of NAND2 high. This causes the output of NAND2 to toggle, with Q becoming high and Q̅ becoming low. 3. When S=0 and R=1: The high input of NAND3 makes its output low, which resets the input of NAND2 to high. The low input of NAND1 makes its output high, which in turn makes the input of NAND2 low. This causes the output of NAND2 to toggle, with Q becoming low and Q̅ becoming high. 4. When S=1 and R=1: Both inputs of NAND1 and NAND3 are low, which means their outputs are high. This makes the input of NAND2 low, which in turn makes its output high. This causes the outputs of NAND1 and NAND3 to toggle, with Q and Q̅ both becoming low. In summary, an SR latch built using two NAND gates can latch and store a single bit of information. The latch operates in two stable states, depending on the values of the S and R inputs. When S=0 and R=0, the latch maintains its previous state. When S=1 and R=0, the latch sets its output to high. When S=0 and R=1, the latch resets its output to low. And when S=1 and R=1, the latch enters an undefined state where both outputs are low.

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