基于FPGA的数字时钟设计

最新推荐文章于 2024-05-08 12:51:16 发布

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最新推荐文章于 2024-05-08 12:51:16 发布

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文章标签： fpga/cpld vhdl

本文链接：https://blog.csdn.net/qq_51116533/article/details/115407449

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基于FPGA的数字时钟设计

芯片与开发板

在这里插入图片描述
技术指标
1.具有正常的日时分秒技术显示功能，用七个数码管分别显示日，时，分，秒。
2.有按键校日，校时，校分，校秒。
3.利用led模拟整点报时功能。
4.起始时间为周一00.00.00。

VHDL代码
分频器

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;

Entity FDIV250 is
  generic(N: integer:=250);       --rate=N，N是偶数
  port(
        clkin: IN std_logic;
        clkout: OUT std_logic
        );
End FDIV250;
Architecture a of FDIV250 is
  signal cnt: integer range 0 to n/2-1;
  signal temp: std_logic;
Begin
  process(clkin)
  begin
      if(clkin'event and clkin='1') then
          if(cnt=n/2-1) then
              cnt <= 0;
              temp <= NOT temp;
          else
              cnt <= cnt+1;
          end if;
      end if;
  end process;
  clkout <= temp;
End a;

D触发器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY D_DD_RS IS
PORT (D,CLOCK:IN STD_LOGIC;
					  Q:OUT STD_LOGIC);
END ENTITY D_DD_RS;

ARCHITECTURE BEHAVIOURAL OF D_DD_RS IS
BEGIN
PROCESS(CLOCK)IS
BEGIN
	IF (CLOCK'EVENT AND CLOCK = '1') THEN
		Q <= D;
	END IF;
END PROCESS;
END;

用D触发器构成的按键消抖电路
在这里插入图片描述
日期计数（7进制）初值1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY DATE IS
PORT (KEYIN,CLK: IN STD_LOGIC;
	 DATE_0: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END;

ARCHITECTURE BHV OF DATE IS
SIGNAL DATE0 :STD_LOGIC_VECTOR(3 DOWNTO 0):="0001";
SIGNAL CLOCK :STD_LOGIC;
BEGIN
CLOCK <= CLK or (not KEYIN);
	PROCESS(CLOCK)
	BEGIN		
		IF(CLOCK'event and CLOCK = '1') THEN 
			IF(DATE0 = 7) THEN
				DATE0 <= "0001";
			ELSE
				DATE0 <= DATE0+1;
			END IF;
		END IF;
	END PROCESS;
DATE_0 <= DATE0;

END;

小时计数（BCD24）初值00

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY HOUR IS
PORT (KEYIN,CLK: IN STD_LOGIC;
	 RCO:OUT STD_LOGIC;
	 hour_1,hour_0: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END;

ARCHITECTURE BHV OF HOUR IS
SIGNAL hour1 :STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
SIGNAL hour0 :STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
SIGNAL CLOCK :STD_LOGIC;
BEGIN
CLOCK <= CLK or (not KEYIN);
 --由于键盘未按下是高电平，所以用非门和或门制作一个触发信号，上升沿进位
	PROCESS(CLOCK)
	BEGIN		
		IF(CLOCK'event and CLOCK = '1') THEN 
			IF(hour1 = 2 AND hour0 = 3) THEN
				hour1 <= "0000";
				hour0 <= "0000";
				RCO <= '1';
			ELSIF (hour0 = 9) THEN
				hour1 <= hour1+1;
				hour0 <= "0000";
			ELSE
				hour0 <= hour0+1;
				RCO <= '0';	
			END IF;
		END IF;
	END PROCESS;
	
	
hour_1 <= hour1;	
hour_0 <= hour0;

END;

分钟计数（BCD60）初值00

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY MIN IS
PORT (CLK,KEYIN: IN STD_LOGIC;
	  RCO:OUT STD_LOGIC;
	 min_1,min_0: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END;

ARCHITECTURE BHV OF MIN IS
SIGNAL min1 :STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
SIGNAL min0 :STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
SIGNAL CLOCK:STD_LOGIC;
BEGIN
CLOCK <= (not KEYIN) or CLK;
	PROCESS(CLOCK)
	BEGIN
		IF(CLOCK'event and CLOCK = '1') THEN 
			IF(min1 = 5 AND min0 = 9) THEN
				min1 <= "0000";
				min0 <= "0000";
				RCO <= '1';
			ELSIF(min0 = 9) THEN 
				min1 <= min1+1;
				min0 <= "0000";				
			ELSE
				min0 <= min0+1;		
				RCO <= '0';		
			END IF;			
		END IF;
	END PROCESS;

min_1 <= min1;	
min_0 <= min0;

END;

秒计数（BCD60）初值00

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY SEC IS
PORT (CLK: IN STD_LOGIC;
	  RCO:OUT STD_LOGIC;
	 sec_1,sec_0: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END;

ARCHITECTURE BHV OF SEC IS
SIGNAL sec1:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
SIGNAL sec0:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
BEGIN
	PROCESS(CLK)
	BEGIN
		IF(CLK'EVENT AND CLK = '1') THEN 
			IF(sec1 = 5 AND sec0 = 9) THEN
				sec1 <= "0000";
				sec0 <= "0000";
				RCO <= '1';
			ELSIF(sec0 = 9) THEN
				sec1 <= sec1+1;
				sec0 <= "0000";
			ELSE 
				sec0 <= sec0+1;
				RCO <= '0';
			END IF;
		END IF;
	END PROCESS;

sec_1 <= sec1;	
sec_0 <= sec0;

END;

选择器（CONTROL）

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY CONTROL IS
PORT (hour_1,hour_0,min_1,min_0,sec_1,sec_0:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	  DD:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
	      Q1,Q2:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END;

ARCHITECTURE BAV OF CONTROL IS
BEGIN		  
	Q1 <= min_0 WHEN DD = "000" ELSE
		  min_1 WHEN DD = "001" ELSE
		  hour_0 WHEN DD = "010" ELSE
		  hour_1 WHEN DD = "011" ELSE
		  "1111";
--由于开发板上只有4位数码管，所以外接延伸两个数码管显示秒的个位十位		  
    Q2 <= sec_0 WHEN DD = "100" ELSE		  
		  sec_1 WHEN DD = "101" ELSE
		  "1111";
END;

译码器（四位共阳极数码管）

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY DUAN IS
PORT (AA: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	  YY:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END;

ARCHITECTURE BAV OF DUAN IS
SIGNAL TEMP:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN 
	PROCESS(AA,TEMP)
	BEGIN
		CASE AA IS
		    WHEN "0000" => TEMP <= "00111111";
			WHEN "0001" => TEMP <= "00000110";
			WHEN "0010" => TEMP <= "01011011";
			WHEN "0011" => TEMP <= "01001111";
			WHEN "0100" => TEMP <= "01100110";
			WHEN "0101" => TEMP <= "01101101";
			WHEN "0110" => TEMP <= "01111101";
			WHEN "0111" => TEMP <= "00000111";
			WHEN "1000" => TEMP <= "01111111";
			WHEN "1001" => TEMP <= "01101111";
			WHEN OTHERS => TEMP <= "00000000";
		END CASE;
		YY <= NOT TEMP;
	END PROCESS;
	END;

译码器（二位共阴极译码器）

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY DUAN2 IS
PORT (AA: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	  YY:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END;

ARCHITECTURE BAV OF DUAN2 IS
SIGNAL TEMP:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN 
	PROCESS(AA,TEMP)
	BEGIN
		CASE AA IS
			WHEN "0000" => TEMP <= "00111111";
			WHEN "0001" => TEMP <= "00000110";
			WHEN "0010" => TEMP <= "01011011";
			WHEN "0011" => TEMP <= "01001111";
			WHEN "0100" => TEMP <= "01100110";
			WHEN "0101" => TEMP <= "01101101";
			WHEN "0110" => TEMP <= "01111101";
			WHEN "0111" => TEMP <= "00000111";
			WHEN "1000" => TEMP <= "01111111";
			WHEN "1001" => TEMP <= "01101111";
			WHEN OTHERS => TEMP <= "00000000";
		END CASE;
		YY <= TEMP;
	END PROCESS;
END;

译码器（一位共阳极译码器）

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY DUAN3 IS
PORT (AA: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	  YY:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END;

ARCHITECTURE BAV OF DUAN3 IS
SIGNAL TEMP:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN 
	PROCESS(AA,TEMP)
	BEGIN
		CASE AA IS
			WHEN "0001" => TEMP <= "00000110";
			WHEN "0010" => TEMP <= "01011011";
			WHEN "0011" => TEMP <= "01001111";
			WHEN "0100" => TEMP <= "01100110";
			WHEN "0101" => TEMP <= "01101101";
			WHEN "0110" => TEMP <= "01111101";
			WHEN "0111" => TEMP <= "01111111"; 
			 --由于时日进制所以第七天显示数字8以模拟‘日’字
			WHEN OTHERS => TEMP <= "00000000";
		END CASE;
		YY <= NOT TEMP;
	END PROCESS;
	END;

报时电路

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY BAOSHI IS
PORT(CLK:IN STD_LOGIC;
	 min_1,min_0,sec_1,sec_0:IN STD_LOGIC_VECTOR(3 DOWNTO 0);  
	 LED:OUT STD_LOGIC);
END;

ARCHITECTURE BAV OF BAOSHI IS
SIGNAL EN:STD_LOGIC;
SIGNAL min1,min0,sec1,sec0:STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

min1 <= min_1;
min0 <= min_0;
sec1 <= sec_1;
sec0 <= sec_0;

	PROCESS(min1,min0,sec1,sec0)
	BEGIN
		IF(min1 = 5 AND min0 = 9 AND sec1 = 5 AND sec0 = 5) THEN
			EN <= '1';
		ELSIF(min1 = 0 AND min0 = 0 AND sec1 = 0 AND sec0 = 0) THEN
			EN <= '0';
		ELSE
			EN <= EN;
		END IF;
	END PROCESS;
	
	PROCESS(EN)
	BEGIN
		IF(EN = '1') THEN 
			LED <= CLK;
		ELSIF(EN = '0') THEN
			LED <= '0';
		ELSE
			LED <= '0';
		END IF;
	END PROCESS;
END;

六进制计数器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CNT5 IS
PORT(CLK: IN STD_LOGIC;
	  Q:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END;

ARCHITECTURE BAV OF CNT5 IS
SIGNAL Q1:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN 
	PROCESS(CLK)
	BEGIN
		IF(CLK'EVENT AND CLK = '1') THEN
			Q1 <= Q1+1;
			IF(Q1 = 5) THEN 
				Q1 <= "000";
			END IF;
		END IF;		
	END PROCESS;
Q <= Q1;
END;

位选

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY WEI IS
PORT (Q: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
	  DD:OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END;

ARCHITECTURE BAV OF WEI IS
BEGIN 
	PROCESS(Q)
	BEGIN
		CASE Q IS
			WHEN "000" => DD <= "001110"; 
			  --外接数码管位选高电平触发，内接数码管位选低电平触发
			WHEN "001" => DD <= "001101";
			WHEN "010" => DD <= "001011";
			WHEN "011" => DD <= "000111";
			WHEN "100" => DD <= "101111";
			WHEN "101" => DD <= "011111";
			WHEN OTHERS => DD <= "001111";
		END CASE;
	END PROCESS;
END;

顶层设计
在这里插入图片描述

文章有参考“思索与猫”《根据VHDL语言制作的数字钟》。

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基于FPGA的数字时钟设计

基于FPGA的数字时钟设计芯片与开发板技术指标1.具有正常的日时分秒技术显示功能，用七个数码管分别显示日，时，分，秒。2.有按键校日，校时，校分，校秒。3.利用led模拟整点报时功能。4.起始时间为周一00.00.00。VHDL代码分频器Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Use ieee.std_logic_arith.all;Entity FDIV250 is
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