verilog编程之路

verilog编程之路

例程一

module mul2port(result_a,//模块名
				result_b,//定义输入输出端口
				din_a,
				din_b,
				din_c,
				din_d,
				sel_a,
				sel_b,
				clk,
				rst_n);
input			[2:0]		din_a;//声明是输入还是输出
input			[1:0]		din_b;
input			[3:0]		din_c;
input			[3:0]		din_d;
input						sel_a;//不写默认是1bits
input						sel_b;
input						clk;
input						rst_n;
output 	[6:0]	result_a;
output 	[5:0]	result_b;
//电路设计完成之后进行信号的定义
reg	[6:0]	result_a;
reg	[5:0]	result_b;
reg [3:0]	sel_dout;

wire [6:0]	result_a_tmp;
wire [5:0]	result_b_tmp;//虽然由本模块产生，但由例化产生，使用wire类型
reg		sel;
always@(posedge clk or negedge rst_n)begin//异步复位时序逻辑
	if(rst_n ==1'b0)beign
	result_b	<= 0;
	end
	else begin
	result_b <=	result_b_tmp;
	end 

always@(posedge clk or negedge rst_n)begin
if(rst_n == 1'b0)begin
	result_a <= 0;
end
else begin
result_a <= result_a_tmp;
	 end
end

//模块的例化
mul_mudule #(.A_W(3),.B_W(4)) mul_4_3(//修改位宽
.mul_a	(din_a),
.mul_b	(sel_dout),
.clk	(clk),
.rst_n	(rst_n),
.mul_result(result_a_tmp)
);
//模块的例化
mul_mudule	#(.A_W(2),.A_W(4))	mul_4_2(
.mul_a (din_b),
.mul_b	(sel_dout),
.clk	(clk),
.rst_n	(rst_n),
.mul_result(result_b_tmp)
);
//选择器,使用组合逻辑进行设计
always@(*)begin
if(sel == 0)
	sel_dout = din_c;
else 
	sel_dout = din_d;
end

//时序逻辑
always@(posedge clk or negedge rst_n)begin
	if(rst_n ==1'b0)beign
	sel	<= 0;
	end
	else begin
	sel	<=	sel_a&sel_b;
	end 
end
endmodule

//描述电路

//计数器自加1
//test.v
module	modlue_name(
		out,
		clk,
		rst_n);
parameter DATA_W  = 4;
input clk;
input rst_n;
output	[DATA_W -1:0]	out;
reg	[DATA_W -1:0]	out;//输出信号reg定义
//中间信号的定义
reg		[DATA_W -1:0]	out_temp;
//组合逻辑电路的设计
always@(*)begin
out_temp = out+1'b1; //组合逻辑的定义
end
//时序逻辑的设计
always@(posedge clk or negedge rst_n)begin
if(rst_n == 1'b0)begin
		out <= 0;
	end
	else begin
	out	 <= 	out_temp;
		end
end
endmodule

//计数器

always@(posedge clk or negedge rst_n)begin
		if(rst_n==1'b0)
				begin
				cnt <=0;
				end
		else  if(add_cnt)
				begin
				if(cnt == 10)
					cnt	<=	0;
				else 
					cnt <= cnt+1;
				end
end