问题:Place 30-494 The design is empty
解决方法:check if opt_design has removed all the leaf cells of your design. Check whether you have instantiated and connected all of the top level ports
检查工程是否只有输入没有输出; 只有输入的工程,添加一个ila可以解决问题。
问题:[DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop.
This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is sdi_0_out_video_in_tuser. Please evaluate your design. The cells in the loop are: sdi_0_out_video_in_tuser_inferred_i_1.
对于wire类型变量来说,不可以将自身赋值给自身
例:wire signed [15:0] S_phase_pll_add;
assign S_phase_pll_add = (S_data_val_cache == 1'b1)?(S_phase_pll + $signed(O_data<<1)):S_phase_pll_add;
这就是导致上述错误的原因
解决方法:
A combinational loop is combinational logic that feeds back to itself without a register. The simplest example is an inverter whose output feeds back to the input creating an oscillator.
问题:[Common 17-55] 'get_property' expects at least one object.
解决方法:修改顶层文件的端口名称后,约束文件还保留修改之前的端口名代码,需要手动删除后,即可解决问题。
问题:[Labtools 27-3733] Error during cs_server initialization: Failed to connect
[Labtools 27-3366] Cannot support older hw_server version 2019.1
[Labtoolstcl 44-494] There is no active target available for server at localhost.
Targets(s) ", jsn-JTAG-SMT2-210251A07952" may be locked by another hw_server.